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sx1272/73 www.semtech.com page 1 wireless, sensing & timing datasheet sx1272/73 - 860 mhz to 1020 mhz low power lo ng range transceiver rev. 3 - march 2015 ?2015 semtech corporation the sx1272/73 transceivers feature the lora tm ? long range modem that provides ultra-long range spread spectrum communication and high interference immunity whilst minimising current consumption. using semtech?s patented lora tm modulation technique sx1272/73 can achieve a sensitiv ity of over -137 dbm using a low cost crystal and bill of materials. the high sensitivity combined with the integrated +20 dbm power amplifier yields industry leading link budg et making it optimal for any application requiring range or robustness. lora tm also provides significant advantages in both blocking and selectivity over conventional modulation techniques, solving the traditional design compromise between range, interference immunity and energy consumption. these devices also support high performance (g)fsk modes for systems including wmbus, ieee802 .15.4g. the sx127 2/73 deliver exceptional phase noise, selectivity, receiver linearity and iip3 fo r significantly lower current consumption than competing devices. part number delivery moq / multiple sx1272imltrt t&r SX1273IMLTRT t&r ? qfn 28 package - operating range from -40 to +85c ? pb-free, halogen free, rohs/weee compliant product ? lora tm modem ? 157 db maximum link budget ? +20 dbm at 100 mw constant rf output vs. v supply ? +14 dbm high efficiency pa ? programmable bit rate up to 300 kbps ? high sensitivity: down to -137 dbm ? bullet-proof front end: iip3 = -12.5 dbm ? 89 db blocking immunity ? low rx current of 10 ma, 100 na register retention ? fully integrated synthesizer with a resolution of 61 hz ? fsk, gfsk, msk, gmsk, lora tm and ook modulation ? built-in bit synchronizer for clock recovery ? preamble detection ? 127 db dynamic range rssi ? automatic rf sense and cad with ultra-fast afc ? packet engine up to 256 bytes with crc ? built-in temperature sensor and low battery indicator ? automated meter reading ? home and building automation ? wireless alarm and security systems ? industrial monitoring and control ? long range irrigation systems general description ordering information 3000 pieces 3000 pieces key product features applications
www.semtech.com page 2 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 1. general description ........................................................................................................ ....................................... 10 1.1. simplified block diagram ................................................................................................. .............................. 10 1.2. product versions ........................................................................................................ ....................................11 1.3. pin diagram .............................................................................................................. ..................................... 11 1.4. pin description ......................................................................................................... ......................................12 1.5. package marking ......................................................................................................... ..................................13 2. electrical characteristics ................................................................................................. ...................................... 14 2.1. esd notice ............................................................................................................... ..................................... 14 2.2. absolute maximum ratings ....................... .......................................................................... .......................... 14 2.3. operating range.......................................................................................................... .................................. 14 2.4. thermal properties ....................................................................................................... ................................. 14 2.5. chip specification ...................................................................................................... ....................................15 2.5.1. power consumption ...................................................................................................... ............................ 15 2.5.2. frequency synthesis.................................................................................................... ............................. 15 2.5.3. fsk/ook mode receiver .................................................................................................. ....................... 16 2.5.4. fsk/ook mode transmitter ............................................................................................... ...................... 17 2.5.5. electrical specification for loratm modu lation ......................................................................... ............... 18 2.5.6. digital specification .................................................................................................. ................................. 20 3. sx1272/73 features......................................................................................................... ..................................... 21 3.1. loratm modem ............................................................................................................. ............................... 22 3.2. fsk/ook modem ............................................................................................................ .............................. 22 4. sx1272/73 digital electronics .............................................................................................. ................................. 23 4.1. the loratm modem ......................................................................................................... ............................ 23 4.1.1. link design using the loratm modem .................................................................................... ................24 4.1.1.1. overview ............................................................................................................. .............................. 24 4.1.1.2. spreading factor..................................................................................................... .......................... 25 4.1.1.3. coding rate .......................................................................................................... ............................ 25 4.1.1.4. signal bandwidth ..................................................................................................... ......................... 26 4.1.1.5. loratm transmission pa rameter relationship ........................................................................... .... 26 4.1.1.6. loratm packet struct ure ............................................................................................. ....................27 4.1.1.7. time on air .......................................................................................................... .............................. 29 4.1.1.8. frequency hopping with loratm........................................................................................ ............. 29 4.1.2. loratm digital interface .............................................................................................. .............................31 4.1.2.1. loratm configuration registers ....................................................................................... ............... 31 4.1.2.2. status registers..................................................................................................... ........................... 31 4.1.2.3. loratm mode fifo data buffer ......................................................................................... ............. 31 4.1.2.4. interrupts in lora mode.............................................................................................. ...................... 32 4.1.3. operation of the loratm modem.......................................................................................... ................... 33 4.1.3.1. operating mode control ............................................................................................... ..................... 33 4.1.4. frequency settings .................................................................................................... ...............................34 4.1.5. frequency error indication ............................................................................................. ........................... 34 4.1.6. loratm modem state machine sequences .................................................................................. ...........35
www.semtech.com page 3 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.6.1. digital io pin mapping ............................................................................................... ....................... 42 4.2. fsk/ook modem ............................................................................................................ .............................. 43 4.2.1. bit rate setting ....................................................................................................... .................................. 43 4.2.2. fsk/ook transmission ................................................................................................... ......................... 44 4.2.2.1. fsk modulation....................................................................................................... .......................... 44 4.2.2.2. ook modulation....................................................................................................... ......................... 44 4.2.2.3. modulation shaping ................................................................................................... ....................... 44 4.2.3. fsk/ook reception ...................................................................................................... ........................... 45 4.2.3.1. fsk demodulator...................................................................................................... ........................ 45 4.2.3.2. ook demodulator...................................................................................................... ....................... 45 4.2.3.3. bit synchronizer ..................................................................................................... ........................... 47 4.2.3.4. frequency error indicator ........................................................................................... ......................48 4.2.3.5. afc .................................................................................................................. ................................. 48 4.2.3.6. preamble detector ................................................................................................... .........................49 4.2.3.7. image rejection mixer ................................................................................................ ...................... 49 4.2.3.8. image and rssi calibration........................................................................................... ................... 49 4.2.3.9. timeout function ..................................................................................................... ......................... 50 4.2.4. operating modes in fsk/ook mode ............. ........................................................................... ................ 50 4.2.5. general overview....................................................................................................... ............................... 50 4.2.6. startup times ......................................................................................................... ...................................51 4.2.6.1. transmitter startup time ............................................................................................. ..................... 51 4.2.6.2. receiver startup time ..................... ........................................................................... ...................... 51 4.2.6.3. time to rssi evaluation .............................................................................................. ..................... 52 4.2.6.4. tx to rx turnaround time ............................................................................................. ................... 53 4.2.6.5. rx to tx............................................................................................................. ................................ 53 4.2.6.6. receiver hopping, rx to rx .......................................................................................... ....................54 4.2.6.7. tx to tx ............................................................................................................. ................................ 54 4.2.7. receiver startup options ............................................................................................... ........................... 54 4.2.8. receiver restart meth ods............................................................................................... .......................... 55 4.2.8.1. restart upon user request ............................................................................................ .................. 55 4.2.8.2. automatic restart after valid packet reception ....................................................................... ......... 55 4.2.8.3. automatic restart when packet collision is dete cted ................................................................. .....56 4.2.9. top level sequencer .................................................................................................... ............................ 56 4.2.9.1. sequencer states..................................................................................................... ......................... 56 4.2.9.2. sequencer transition s ................................................................................................ ...................... 57 4.2.9.3. timers ............................................................................................................... ................................ 58 4.2.9.4. sequencer state machine .................. ........................................................................... ....................60 4.2.10. data processing in fsk/ook mode ....................................................................................... ................ 62 4.2.10.1. block diagram ....................................................................................................... .......................... 62 4.2.10.2. data operation modes ................................................................................................ .................... 62 4.2.11. fifo ................................................................................................................. .......................................63 4.2.11.1. sync word recognition............................................................................................... .................... 64
www.semtech.com page 4 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.12. digital io pins mapping .............................................................................................. .............................66 4.2.13. continuous mode ...................................................................................................... ..............................67 4.2.13.1. general description ................................................................................................. ....................... 67 4.2.13.2. tx processing ....................................................................................................... .......................... 67 4.2.13.3. rx processing ....................................................................................................... .......................... 68 4.2.14. packet mode ........................................................................................................... ................................ 68 4.2.14.1. general description ................................................................................................. ....................... 68 4.2.14.2. packet format ....................................................................................................... .......................... 69 4.2.14.3. tx processing ....................................................................................................... .......................... 72 4.2.14.4. rx processing ....................................................................................................... .......................... 72 4.2.14.5. handling large packets .............................................................................................. .................... 73 4.2.14.6. packet filtering .................................................................................................... ........................... 73 4.2.14.7. dc-free data mechanisms.................. ........................................................................... ................ 75 4.2.14.8. beacon tx mode ...................................................................................................... ....................... 76 4.2.15. io-homecontrol? compatibility mode .................................................................................... .................. 76 4.3. spi interface ........................................................................................................... .......................................77 5. sx1272/73 analog & rf frontend electronics. ................................................................................ ..................... 79 5.1. power supply strategy .................................................................................................... .............................. 79 5.2. low battery detector ..................................................................................................... ................................ 79 5.3. frequency synthesis ...................................................................................................... ............................... 79 5.3.1. crystal oscillator ..................................................................................................... .................................. 79 5.3.2. clkout output .......................................................................................................... .............................. 80 5.3.3. pll .................................................................................................................... ........................................ 80 5.3.4. rc oscillator .......................................................................................................... ................................... 82 5.4. transmitter description ................................................................................................. .................................83 5.4.1. architecture description ............................................................................................... ............................. 83 5.4.2. rf power amplifiers.......................... .......................................................................... .............................. 83 5.4.3. high power +20 dbm operation ........................................................................................... .................... 84 5.4.4. over current protection ............................................................................................... .............................85 5.5. receiver description..................................................................................................... ................................. 85 5.5.1. overview ............................................................................................................... .................................... 85 5.5.2. receiver enable d and receiver active st ates............................................................................ .............. 85 5.5.3. automatic gain control in fsk/ook mode ................................................................................. ............. 86 5.5.4. rssi in fsk/ook mode ................................................................................................... ........................ 87 5.5.5. rssi and snr in loratm mode............................................................................................ .................. 88 5.5.6. channel filter ......................................................................................................... ................................... 89 5.5.7. temperature measuremen t................................................................................................ ....................... 89 6. description of the registers..................... .......................................................................... .................................... 91 6.1. register table summary ................................................................................................... ............................ 91 6.2. fsk/ook mode register map ............................................................................................... ........................94 6.3. loratm mode register map................................................................................................. ...................... 108 7. application information .. .................................................................................................. .................................... 115
www.semtech.com page 5 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.1. crystal resonator specification.......................................................................................... ......................... 115 7.2. reset of the chip ........................................................................................................ ................................. 115 7.2.1. por.................................................................................................................... ..................................... 115 7.2.2. manual reset .......................................................................................................... ................................116 7.3. top sequencer: listen mode examples .......... ............................................................................ ................ 116 7.3.1. wake on preamble interrupt ................. ............................................................................ ...................... 116 7.3.1.1. timing diagram ....................................................................................................... ........................ 117 7.3.1.2. sequencer configurat ion ............................................................................................. ...................118 7.3.2. wake on syncaddress in terrupt ......................................................................................... .....................119 7.3.2.1. timing diagram ....................................................................................................... ........................ 119 7.3.2.2. sequencer configurat ion .............................................................................................. .................. 120 7.4. top sequencer: beacon mode .............................................................................................. ......................122 7.4.1. timing diagram......................................................................................................... ............................... 122 7.4.2. sequencer configuration................................................................................................ ......................... 122 7.5. example crc calculation ................................................................................................. ..........................124 7.6. example temperature reading ............................................................................................. ......................125 8. packaging information ............................. ......................................................................... ................................... 126 8.1. package outline drawing .......................... ........................................................................ .......................... 126 8.2. recommended land pattern ................................................................................................. ...................... 127 8.3. tape and reel informat ion ............................................................................................... ...........................128 9. revision history........................................................................................................... ........................................ 129
www.semtech.com page 6 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation table 1. sx1272/73 device variants and key paramete rs ........................................................................ ...................11 table 2. pin description ..................................................................................................... ...........................................12 table 3. absolute maximum ratings ................. ........................................................................... .................................14 table 4. operating range ..................................................................................................... ........................................14 table 5. operating range ..................................................................................................... ........................................14 table 6. power consumption specification ....... .............................................................................. ..............................15 table 7. frequency synthesizer specification .. ............................................................................... .............................15 table 8. receiver specification .............................................................................................. .......................................16 table 9. transmitter specific ation ........................................................................................... ......................................17 table 10. electrical specifications: loratm mode ............................................................................. ............................18 table 11. digital specification ..................... ......................................................................... .........................................20 table 12. example loratm modem performances .................................................................................. ...................23 table 13. range of spreading factors .............. ........................................................................... .................................25 table 14. cyclic coding overhead ............................................................................................. ...................................25 table 15. loratm operating mode functionality ................................................................................ .........................33 table 16. lora cad consumption figures ......... .............................................................................. ...........................42 table 17. dio mapping loratm mode ............................................................................................ .............................42 table 18. bit rate examples .................................................................................................. .......................................43 table 19. preamble detector settings ............... .......................................................................... ..................................49 table 20. rxtrigger settings to enable timeout in terrupts .................................................................... ......................50 table 21. basic transceiver modes .................. .......................................................................... ..................................50 table 22. receiver startup time summary ...................................................................................... ............................52 table 23. receiver startup op tions ........................................................................................... ...................................55 table 24. sequencer states . .................................................................................................. .......................................56 table 25. sequencer tran sition options ....................................................................................... ................................57 table 26. sequencer ti mer settings ........................................................................................... ..................................59 table 27. status of fifo when switching between differ ent modes of the chip .................................................. .......64 table 28. dio mapping, continuous mode ....... ................................................................................ ............................66 table 29. dio mapping, packet mode ........................................................................................... ...............................66 table 30. crc description ................................................................................................... ........................................74 table 31. power amplifie r mode selection truth table ......................................................................... .......................83 table 32. high power settings ................................................................................................ ......................................84 table 33. operating range, +20 dbm operation . ................................................................................ .........................84 table 34. operating range, +20 dbm operation . ................................................................................ .........................84 table 35. trimming of the ocp current ........................................................................................ ................................85 table 36. lna gain control and performances .................................................................................. ..........................86 table 37. rssismoothing option s .............................................................................................. ...................................88 table 38. available rxbw settings ............................................................................................ ....................................89 table 39. registers summary .................................................................................................. .....................................91
www.semtech.com page 7 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation table 40. register map ....................................................................................................... ..........................................94 table 41. register map, lora mode .............. .............................................................................. ...............................108 table 42. crystal specification .............................................................................................. ......................................115 table 43. listen mode with preamb ledetect condition settings ................................................................. ................118 table 44. listen mode with preamble detect condition recommended dio mapping ...............................................118 table 45. listen mode with synca ddress condition settings ............... ..................................................... .................120 table 46. listen mode with preamble detect condition recommended dio mapping ...............................................121 table 47. beacon mode settings ............................................................................................... .................................123 table 48. revision history ................................................................................................... ........................................129
www.semtech.com page 8 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 1. sx1272/73 block diagram ................ ........................................................................... .................................10 figure 2. pin diagram ....................................................................................................... ............................................11 figure 3. package marking ................................................................................................... ........................................13 figure 4. simplified sx1272 block schematic dia gram ......................................................................... ......................21 figure 5. loratm modem connectivity ........ ................................................................................. ..............................24 figure 6. loratm packet stru cture ........................................................................................... ..................................27 figure 7. interrupts gene rated in the case of successful frequency hopping communication. ................................... ..30 figure 8. loratm data buffer .................... ............................................................................ ......................................31 figure 9. applied versus measur ed frequency offset and influence on per. .................................................... ..........34 figure 10. loratm modulation transmission sequence. ......................................................................... ....................35 figure 11. loratm receive se quence. ......................................................................................... ...............................36 figure 12. loratm cad flow ..................... ............................................................................. .....................................40 figure 13. channel activity detection (cad) time as a function of sp reading factor. ......................................... ..........41 figure 14. consumption profile of the lora cad process ...................................................................... ....................42 figure 15. ook peak demodula tor description ................................................................................. ..........................45 figure 16. floor threshold op timization ..................................................................................... .................................46 figure 17. bit synchronizer description ..................................................................................... ..................................47 figure 18. startup process .................................................................................................. .........................................51 figure 19. time to rssi sa mple .............................................................................................. .....................................52 figure 20. tx to rx turnar ound .............................................................................................. .....................................53 figure 21. rx to tx turnaround ................. ............................................................................. .....................................53 figure 22. receiver hoppin g ................................................................................................. .......................................54 figure 23. transmitter hopping .................. ............................................................................ ......................................54 figure 24. timer1 and timer2 mechanism ....... ............................................................................... .............................58 figure 25. sequencer state machine .......................................................................................... .................................60 figure 26. sx1272/73 data proces sing conceptual view ........................................................................ ...................62 figure 27. fifo and shift register (sr) ..................................................................................... .................................63 figure 28. fifolevel irq source behavior .... ................................................................................ ...............................64 figure 29. sync word recognition ............................................................................................ ...................................65 figure 30. continuous mode conceptual view .................................................................................. ..........................67 figure 31. tx processing in continuous mode ................................................................................. ............................67 figure 32. rx processing in continuous mode ................................................................................. ...........................68 figure 33. packet mode conceptual view .... .................................................................................. .............................69 figure 34. fixed length packet format ........... ............................................................................ ................................70 figure 35. variable length pa cket format .................................................................................... ...............................71 figure 36. unlimited length pa cket format ................................................................................... ..............................71 figure 37. manchester encodi ng/decoding ..................................................................................... ............................75 figure 38. data whitening po lynomial ........................................................................................ .................................76 figure 39. spi timing diagram (single access) ............................................................................... ............................77
www.semtech.com page 9 section page table of contents sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 40. tcxo connection ..................... ............................................................................. .....................................79 figure 41. typical phase noise perf ormances of the low cons umption and low phase noise plls. ......................81 figure 42. rf front-end architectu re shows the internal pa configuration. ................................................... ............83 figure 43. receiver block dia gram ........................................................................................... ...................................86 figure 44. agc steps definition ............................................................................................. .....................................87 figure 45. temperature sensor response ......... ............................................................................. ............................90 figure 46. por timing diagram ...................... ......................................................................... .................................115 figure 47. manual reset timi ng diagram ...................................................................................... ............................116 figure 48. listen mode: prin ciple ........................................................................................... ....................................116 figure 49. listen mode with no preamble received .................... ........................................................ .....................117 figure 50. listen mode with preamble received ............................................................................... ........................117 figure 51. wake on pr eambledetect state machine ............................................................................. ....................118 figure 52. listen mode with no syncaddress detected ......................................................................... ....................119 figure 53. listen mode with pr eamble received and no syncaddress ............................................................ .........119 figure 54. listen mode with pr eamble received & valid syncaddress . .......................................................... .........120 figure 55. wake on syncaddres s state machine ................................................................................ .....................120 figure 56. beacon mode timing diagram ........... ............................................................................ ...........................122 figure 57. beacon mode state machine ........................................................................................ ............................122 figure 58. example crc code ................................................................................................. .................................124 figure 59. example temperatur e reading ...................................................................................... ..........................125 figure 60. package outline drawing .......................................................................................... ................................126 figure 61. recommended land pattern ......................................................................................... ...........................127 figure 62. tape and reel in formation ........................................................................................ ................................128
www.semtech.com page 10 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 1. general description the sx1272/73 incorporates the lora tm ? spread spectrum modem which is capable of achieving signific antly longer range than existing systems based on fsk or ook modulation. with this new modulation scheme se nsitivities 8 db better than equivalent data rate fsk can be achieved with a low-cost, lo w-tolerance crystal reference. this increase in link budget provides much longer range and robustness without the need for a tcxo or external amplification. lora tm also provides significant advances in select ivity and blocking perf ormance, further improving communication reliability. for maximum flexibility the user may decide on the spre ad spectrum modulation bandwidth (b w), spreading factor (sf) and error correction rate (cr). another benefit of the spread modulation is that each spread ing factor is orthog onal - thus multiple transmitted signals can occupy the same ch annel without interfering. this also pe rmits simple coexistence with existing fsk based systems. standard gfsk, fsk, ook, and gmsk modulation is also provided to allow compatibility with existing systems or standards such as wireless mbus and ieee 802.15.4g. the sx1272 offers three bandwidth options of 125 khz, 250 khz, and 500 khz with spreading factors ranging from 6 to 12. t he sx1273 offers the same bandwidth options with spreading factors from 6 to 9. 1.1. simplified block diagram figure 1. sx1272/73 block diagram
www.semtech.com page 11 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 1.2. product versions the features of the two product variants sx1272 and sx1273 are detailed in the following table. table 1 sx1272/73 device variants and key parameters part number frequency range lora tm ? parameters spreading factor bandwidth effective bitrate sensitivity 1.3. pin diagram the following diagram shows the pin arrangement of the qfn package, top view. figure 2. pin diagram sx1272 860 - 1020 mhz 6 - 12 125 - 500 khz 0.24 - 37.5 kbps -117 to -137 dbm sx1273 860 - 1020 mhz 6 - 9 125 - 500 khz 1.7 - 37.5 kbps -117 to -130 dbm
www.semtech.com page 12 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 1.4. pin description table 2 number name type description - exposed ground pad - supply voltage - regulated supply voltage for analogue circuitry - regulated supply voltage for digital blocks i/o xtal connection or tcxo input i/o xtal connection i/o reset trigger input - can be connected to ground - can be connected to ground i/o digital i/o, software configured i/o digital i/o, software configured i/o digital i/o, software configured i/o digital i/o, software configured i/o digital i/o, software configured i/o digital i/o, software configured - supply voltage - ground i spi clock input o spi data output i spi data input i spi chip select input o nc o ground o rx/tx switch cont rol: high in tx o rf output i rf input o ground o optional high-power pa output o regulated supply for the pa pin description 0 ground 1v b a t 1 2v r _ a n a 3 vr_dig 4x t a 5x t b 6 reset 7n c 8n c 9d i o 0 10 dio1/dclk 11 dio2/data 12 dio3 13 dio4 14 dio5 15 vbat2 16 gnd 17 sck 18 miso 19 mosi 20 nss 21 rf_mod 22 gnd 23 rxtx 24 rfo 25 rfi 26 gnd 27 pa_boost 28 vr_pa
www.semtech.com page 13 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 1.5. package marking figure 3. package marking
www.semtech.com page 14 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 2. electrical characteristics 2.1. esd notice the sx1272/73 is a high performance radio frequency device. it satisfies: ? class ii of the jedec standard jesd22-a114-b (human body model) on all pins. ? class iii of the jedec standard jesd22-c101c (charged device m odel) on all pins it should thus be handled with all the necessary esd precautions to avoid any permanent damage. 2.2. absolute maximum ratings stresses above the values listed below may cause permanent device failure. exposure to absolute maximum ratings for extended periods may af fect device reliability. table 3 absolute maximum ratings symbol description min max unit vddmr supply voltage -0.5 3.9 v tmr temperature -55 +115 c tj junction temperature - +125 c pmr rf input level - +10 dbm note specific ratings apply to +20 dbm operation (see section 5.4.3). 2.3. operating range table 4 operating range symbol description min max unit vddop supply voltage 1.8 3.7 v to p operational temperature range -40 +85 c clop load capacitance on digital ports - 25 pf ml rf input level - +10 dbm note a specific supply voltage range applies to +20 dbm operation (see section 5.4.3). 2.4. thermal properties table 5 operating range symbol description min typ max unit theta_ja package ? ja (junction to ambient) - 22.185 - c/w theta_jc package ? jc (junction to case ground paddle) - 0.757 - c/w
www.semtech.com page 15 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 2.5. chip specification the tables below give the electrical specifications of th e transceiver under the following conditions: supply voltage vbat1 = vbat2 = vdd = 3.3 v, temperature = 25 c, fxosc = 32 mhz, f rf = 915 mhz, pout = +13 dbm, 2 level fsk modulation without p re-filtering, fda = 5 khz, bit rate = 4.8 kbps and terminated in a matched 50 ohm impedance, unless otherwise specified. shared rx and tx path matching. note unless otherwise specified, the performance in the 868 mhz band is identical or better. 2.5.1. power consumption table 6 symbol description conditions min typ max unit iddsl supply current in sleep mode - 0.1 1 ua iddidle supply current in idle mode rc oscillator enabled - 1.5 - ua iddst supply current in standby mode crystal oscillator enabled - 1.4 1.6 ma iddfs supply current in synthesizer mode fsrx - 4.5 - ma iddr supply current in receive mode lnaboost of f lnaboost on - - 10.5 11.2 - - ma iddt supply current in transmit mode wi th impedance matching rfop = +20 dbm on pa_boost rfop = +17 dbm on pa_boost rfop = +13 dbm on rfo pin rfop = + 7 dbm on rfo pin - - - - 125 90 28 18 - - - - ma ma ma ma power consumption specification 2.5.2. frequency synthesis table 7 frequency synthesizer specification symbol description conditions min typ max unit frf synthesizer frequency range programmable 860 - 1020 mhz fxosc crystal oscillator frequency - 32 - mhz ts_osc crystal oscillator wake-up time - 250 - us ts_fs frequency synthesizer wake-up time to plllock signal from standby mode - 60 - us ts_hop frequency synthesizer hop time a t most 10 khz away from the tar - get frequency 200 khz step 1 m hz step 5 mhz step 7 mhz step 12 mhz step 20 mhz step 25 mhz step - - - - - - - 20 20 50 50 50 50 50 - - - - - - - us us us us us us us fstep frequency synthesizer step fstep = fxosc/2 19 - 61.0 - hz frc rc oscillator frequency after calibration - 62.5 - khz
www.semtech.com page 16 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation note for maximum bit rate the maximum modulation index is 0.5. 2.5.3. fsk/ook mode receiver all receiver tests are performed with rxbw = 10 khz (single side bandwidth) as programmed in regrxbw , receiving a pn15 sequence. sensitivities are reported for a 0.1% ber ( with bit synchronizer enabled), unless otherwise specified. blocking tests are performed with an unmodulated interferer. the wanted signal power for the blocking immunity, acr, iip2, iip3 and amr tests is set 3 db above the receiver sensitivity level. table 8 receiver specification brf bit rate, fsk programmable values (1) 1.2 - 300 kbps bro bit rate, ook programmable 1.2 - 32.768 kbps bra bit rate accuracy abs(wanted br - available br) - - 250 ppm fda frequency deviation, fsk (1) programmable fda + brf/2 =< 250 khz 0.6 - 200 khz symbol description conditions min typ max unit rfs_f direct tie of rfi and rfo pins, shared rx, tx paths fsk sensitiv - ity, highest lna gain. fda = 5 khz, br = 1.2 kbps fda = 5 khz, br = 4.8 kbps fda = 40 khz, br = 38.4 kbps* fda = 20 khz, br = 38.4 kbps** fda = 62.5 khz, br = 250 kbps*** - - - - - -119 -115 -105 -106 -92 - - - - - dbm dbm dbm dbm dbm split rf paths, lnaboost is turned on, the rf switch insertion loss is not accounted for. fda = 5 khz, br = 1.2 kbps fda = 5 khz, br = 4.8 kbps fda = 40 khz, br = 38.4 kbps* fda = 20 khz, br = 38.4 kbps** fda = 62.5 khz, br = 250 kbps*** - - - - - -123 -119 -110 -110 -97 - - - - - dbm dbm dbm dbm dbm rfs_o ook sensitivity, highest lna gain shared rx, tx paths br = 4.8 kbps br = 32 kbps - - -117 -108 - - dbm dbm ccr co-channel rejection - -9 - db acr adjacent channel rejection fda = 2 khz, br = 1.2 kbps, rxbw = 5.2 khz offset = +/- 25 khz - 54 - db fda = 5 khz, br=4.8kbps offset = +/- 25 khz offset = +/- 50 khz - - 50 50 - - db db bi blocking immunity offset = +/- 1 mhz offset = +/- 2 mhz offset = +/- 10 mhz - - - 73 78 87 - - - db db db amr am rejection, am modulated interferer with 100% modulation depth, fm = 1 khz, square offset = +/- 1 mhz offset = +/- 2 mhz offset = +/- 10 mhz - - - 73 78 87 - - - db db db
www.semtech.com page 17 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation * rxbw = 83 khz (single side bandwidth) ** rxbw = 50 khz (single side bandwidth) *** rxbw = 250 khz (single side bandwidth) 2.5.4. fsk/ook mode transmitter table 9 transmitter specification iip2 2nd order input intercept point unwanted tones are 20 mhz above the lo highest lna gain - +57 - dbm iip3 3rd order input intercept point unwanted tones are 1 mhz and 1.995 mhz above the lo highest lna gain g1 lna gain g2, 4db sensitivity reduction. - - -12.5 -8.5 - - dbm dbm bw_ssb single side channel filter bw programmable 2.7 - 250 khz imr image rejection wanted signal power sensitivity +3 db ber = 0.1% - 48 - db ima image attenuation - 57 - db dr_rssi rssi dynamic range agc enabled min max - - -127 0 - - dbm dbm symbol description conditions min typ max unit rf_op rf output power in 50 ohms on rfo pin (high efficiency pa). programmable with steps max min +11 - +14 -1 - - dbm dbm
www.semtech.com page 18 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 2.5.5. electrical specification for lora tm modulation the table below gives the electrical specific ations for the transceiver operating with lora tm modulation. following conditions apply unless otherwise specified: ? supply voltage = 3.3 v. ? temperature = 25 c. ? f xosc = 32 mhz. ? band: f rf = 915 mhz. ? bandwidth (bw) = 125 khz. ? spreading factor (sf) = 12. ? error correction code (ec) = 4/6. ? packet error rate (per)= 1% ? crc on payload enabled. ? output power = 13 dbm in transmission. ? payload length = 10 bytes. ? preamble length = 12 symbols (programmed register preamblelength=8 ) ? with matched impedances acp transmitter adjacent channel power (measured at 25 khz offset) bt = 1. measurement conditions as defined by en 300 220-1 v2.3.1 - - -37 dbm ts_tr transmitter wake up time, to the first rising edge of dclk frequency synthesizer enabled, paramp = 10 us, br = 4.8 kbps - 120 - us symbol description conditions min. typ max unit iddr_l supply current in receiver lora tm mode lnaboost off, bw = 125 khz lnaboost off, bw = 250 khz lnaboost off, bw = 500 khz - - - 9.7 10.5 12 - - - ma ma ma lnaboost on, bw = 125 khz lnaboost on, bw = 250 khz lnaboost on, bw = 500 khz - - - 10.8 11.6 13 - - - ma ma ma iddt_l supply current in transmitter mode rfop = 13 dbm rfop = 7 dbm - - 28 18 - - ma ma iddt_h_l supply current in transmitter mode with an external impedance transformation using pa_boost pin rfop = 17 dbm -90-ma bi_l blocking immunity, frf=868 mhz cw interferer offset = +/- 1 mhz offset = +/- 2 mhz offset = +/- 10 mhz - 82.5 86.5 89 db db db iip3_l 3rd order input intercept point, highest lna gain, frf=868 mhz, cw interferer f1 = frf + 1 mhz f2 = frf + 1.995 mhz - -12.5 - dbm table 10 electrical specifications: lora tm mode
www.semtech.com page 19 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation iip2_l 2nd order input intercept point, highest lna gain, frf = 868 mhz, cw interferer. f1 = frf + 20 mhz f2 = frf+ 20 mhz + ' f -57-dbm br_l bit rate, long-range mode from sf6, cr = 4/5, bw = 500 khz to sf12, cr = 4/8, bw = 125 khz 0.24 - 37.5 kbps rfs_l125 rf sensitivity, long-range mode, highest lna gain, lna boost, 125 khz bandwidth using split rx/tx path sf = 6 sf = 7 sf = 8 sf = 9 sf = 10 sf = 11 sf = 12 - - - - - - - -121 -124 -127 -130 -133 -135 -137 - - - - - - - dbm dbm dbm dbm dbm dbm dbm rfs_l250 rf sensitivity, long-range mode, highest lna gain, lna boost, 250 khz bandwidth using split rx/tx path sf = 6 sf = 7 sf = 8 sf = 9 sf = 10 sf = 11 sf = 12 - - - - - - - -118 -122 -125 -128 -130 -132 -135 - - - - - - - dbm dbm dbm dbm dbm dbm dbm rfs_l500 rf sensitivity, long-range mode, highest lna gain, lna boost, 500 khz bandwidth using split rx/tx path sf = 6 sf = 7 sf = 8 sf = 9 sf = 10 sf = 11 sf = 12 - - - - - - - -111 -116 -119 -122 -125 -128 -129 - - - - - - - dbm dbm dbm dbm dbm dbm dbm ccr_lcw co-channel rejection single cw tone = sens +6 db 1% per sf = 7 sf = 8 sf = 9 sf = 10 sf = 11 sf = 12 - - - - - - 5 9.5 12 14.4 17 19.5 - - - - - - db db db db db db ccr_ll co-channel rejection interferer is a lora tm signal using same bw and same sf. pw = sensitivity +3 db -6 db acr_lcw adjacent channel rejection frf = 868 mhz interferer is 1.5*bw_l from the wanted signal center frequency 1% per, single cw tone = sensitivity + 3 db sf = 7 sf = 12 - - 60 72 - - db db imr_lcw image rejection after calibration 1% per, single cw tone = sens +3 db -66-db ferr_l maximum tolerated frequency offset between transmitter and receiver, no sensitivity degradation bw_l = 125 khz bw_l = 250 khz bw_l = 500 khz -30 -60 -120 - - - 30 60 120 khz khz khz symbol description conditions min. typ max unit table 10 electrical specifications: lora tm mode
www.semtech.com page 20 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 2.5.6. digital specification conditions: temp = 25 c, vdd = 3.3 v, fx osc = 32 mhz, unless otherwise specified. table 11 symbol description conditions min typ max unit v ih digital input level high 0.8 - - vdd v il digital input level low - - 0.2 vdd v oh digital output level high imax = 1 ma 0.9 - - vdd v ol digital output level low imax = -1 ma - - 0.1 vdd f sck sck frequency - - 10 mhz t ch sck high time 50 - - ns t cl sck low time 50 - - ns t rise sck rise time - 5 - ns t fall sck fall time - 5 - ns t setup mosi setup time from mosi change to sck rising edge 30 - - ns t hold mosi hold time from sck rising edge to mosi change 20 - - ns t nsetup nss setup time from nss falling edge to sck rising edg e 30 - - ns t nhold nss hold time from sck falling edge to nss rising edg e, normal mode 100 - - ns t nhigh nss high time between spi accesses 20 - - ns t_data data hold and setup time 250 - - ns digital specification
www.semtech.com page 21 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 3. sx1272/73 features this section gives a high-level overview of the functionality of the sx1272/73 lo w-power, highly integrated transceiver. the following figure shows a simplified block diagram of the sx1272/73. figure 4. simplified sx 1272 block schematic diagram sx1272/73 is a half-duplex, low-if transceiver. here the receiv ed rf signal is first amplified by the lna. the lna input is single ended to minimize the external bom and for ease of design. following the lna output, the conversion to differential is made to improve the second order linearity and harmonic re jection. the signal is then down-converted to in-phase and quadrature (i&q) components at the intermediate frequency (if) by the mixer stage. a pair of sigma delta adcs then perform data conversion, with all subsequent signal proce ssing and demodulation performed in the digital domain. the digital state machine also controls the automatic frequency co rrection (afc), received signal strength indicator (rssi) and automatic gain control (agc). it also features the higher-l evel packet and protocol level functionality of the top level sequencer (tls). the frequency synthesizer gene rates the local oscillator (lo) frequency for both receiver and transmitter. the pll is optimized for user-transparent low lock time and fast auto-c alibrating operation. in transmission, frequency modulation is performed digitally within the pll bandwidth. the pll also feat ures optional prefiltering of the bit stream to improve spectral purity. sx1272/73 feature a pair of rf power amplifiers. the first, co n nected to rfo, can deliver up to +14 dbm, is unregulated for high power efficiency and can be connected directly to the rf receiver input via a pair of passive components to form a single antenna port high efficiency transceiver. the second pa, connected to the pa_boost pin, can deliver up to +20 dbm via a dedicated matching network. sx1272/73 also includes two timing references, an r c oscillator and a 32 mhz crystal oscillator. all major parameters of the rf front end and digital state machine are fully configurable via an spi interface which gives a ccess to sx1272/73?s configuration registers. this includes a mode auto sequencer that oversees the transition and calibration of the sx1272/73 between intermediate mo des of operation in the fastest time possible.
www.semtech.com page 22 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the sx1272/73 are equipped with both standard fsk and long range spread spectrum ( lora tm ) modems. depending upon the mode selected either conventional ook or fsk modulation may be employed or the lora tm spread spectrum modem. 3.1. lora tm modem the lora tm modem uses a proprietary spread spectrum modulation technique. this modulation, in contrast to legacy modulation techniques, permits an increase in link budget and increased immunity to in-band interference. at the same time the frequency tolerance re quirement of the crystal refere nce oscillator is relaxed - allo wing a performanc e increase for a reduction in system cost. for a fuller description of the desi gn trade-offs and o peration of the sx1272 /73 please consult section 4.1 of the datasheet. 3.2. fsk/ook modem in fsk/ook mode the sx1272/73 supports standard modula tion techniques including ook, fsk, gfsk, msk and gmsk. the sx1272/73 is especially suited to narrow band co mmunication thanks the low-if architecture employed and the built-in afc functionality. fo r full information on the fsk/ook modem please consult section 4.2 of this document.
www.semtech.com page 23 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4. sx1272/73 digital electronics 4.1. the lora tm modem the lora tm modem uses spread spectrum modulation and forward error correction techniques to increase the range and robustness of radio communication links compared to tradi tional fsk or ook based modulation. examples of the performance improvement possible for several settings are su mmarised in the table below. the spreading factor and error correction rate are design variables that allow the designer to optimise the trade-off between occupied bandwidth, data rate, link budget improvement and immunity to interferen ce. in the table below a coding rate of 4/5 is used. table 12 bandwidth (khz) spreading factor nominal rb (bps) sensitivity (dbm) 125 6 9380 -122 125 12 293 -137 250 6 18750 -119 250 12 586 -134 500 6 3750 -116 500 12 1172 -131 example lora tm modem performances typically such performance gains requir e high stability frequ ency references, with lora tm this is not the case. low crystal tolerances are easily accommodated reducing the overall bom cost for a given increase in link budget. for european operation the range of crystal tolerances accept ab le for each sub-band (of the erc 70-03) is given in the specifications table. for us based operation a frequency hopping mode is availabl e that automates both the lora tm spread spectrum and frequency hopping spread spectrum processes. another important facet of the lo ra tm modem is its increased immu nity to interference. the lora tm ? modem is capable of co-channel gmsk rejection of up to 25 db. this immunity to interference permits the simple coexistence of lora tm modulated systems either in bands of heavy spectral usage or in hybrid communi cation networks that use lora tm to extend range when legacy modulation schemes fail.
www.semtech.com page 24 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.1. link design using the lora tm modem 4.1.1.1. overview the lora tm modem is setup as shown in the following figure. this configuration permits the simple replacement of the fsk modem with the lora tm modem via the configuration register setting regopmode. this change can be performed on the fly (in sleep operating mode) thus permi tting the use of both standard fsk or ook in conjunction with the long range capability. the lora tm modulation and demodulation process is proprietary, it uses a form of spread spectrum modulation combined with cyclic error correction coding. the combined influe nce of these two factors is an increase in link budget and enhanced immunity to interference. figure 5. lora tm modem connectivity a simplified outline of the transmit and receive proce sses is also shown above. here we see that the lora tm modem has an independent dual port data buffer fifo that is accessed through an spi interf ace common to all modes. upon selection of lora tm mode, the configuration register mappi ng of the sx1272/73 changes. for full details of this change please consult the register description of section 6 . so that it is possible to optimise the lo ra tm modulation for a given application, access is given to the designer to three critical design parameters. each one permitting a trade off between link budget, immunity to interference, spectral occupancy and nominal data rate. these parameters are spreading factor, modulation bandwidth and error coding rate.
www.semtech.com page 25 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.1.2. spreading factor the spread spectrum lora tm ? modulation is performed by representing each bit of payload information by multiple chips of information. the rate at which the spread informatio n is sent is referred to as the symbol rate ( rs ), the ratio between the nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information. the range of values accessible with the lora tm modem are shown in the following table. table 13 range of spreading factors spreadingfactor (regmodemconfig2) spreading factor (chips / symbol) lora demodulator snr 6 64 -5 db 7 128 -7.5 db 8 256 -10 db 9 512 -12.5 db 10 1024 -15 db 11 2048 -17.5 db 12 4096 -20 db note that the spreading factor, spreadingfactor , must be known in advance on both transmit and receive sides of the link as different spreading factors are orthogonal to each other. note also the resulting signal to noise ratio (snr) required at the receiver input. it is the capability to receive signals with negative snr th at increases the sensit ivity, so link budget an d range, of the lora receiver. spreading factor 6 sf = 6 is a special use case for the highest data rate tr ansmission p ossible with the lora modem. to this end several settings must be activated in the sx1272/73 registers when it is in use. these settings are only valid for sf6 and should be set back to their default values for other spreading factors: ? set spreadingfactor = 6 in regmodemconfig2 ? the header must be set to implicit mode. ? set the bit field detectionoptimize of register regloradetectoptimize to value "0b101". ? write 0x0c in the register regdetectionthreshold . 4.1.1.3. coding rate to further improve the robustness of the link the lora tm modem employs cyclic error coding to perform forward error detection and correction. such error coding incurs a transmission overhead - the resultant additional data overhead per transmission is shown in the table below. table 14 codingrate (regmodemconfig1) cyclic coding rate overhead ratio 1 4/5 1.25 2 4/6 1.5 3 4/7 1.75 4 4/8 2 cyclic coding overhead
www.semtech.com page 26 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation forward error correction is part icularly efficient in improving the reliability of the link in the presence of interference. so that the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can optionally be included in the packet header for use by the receiver. please consult section 4.1.1.6 for more information on the lora tm packet and header. 4.1.1.4. signal bandwidth an increase in signal bandwidth permits the use of a higher ef fective data rate, thus reduc ing transmission time at the expense of reduced sensitivity improvement. there are of course regulatory constraints in most countries on the permissible occupied bandwidth. contrary to the fsk modem, which is described in terms of the single sideband bandwidth, the lora tm ? modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). the range of bandwidths relevant to most regulatory situations is given in the lora tm ? modem specifications table (see section 2.5.5 ). bandwidth (khz) spreading factor coding rate nominal rb (bps) sensitivity (dbm) 125 12 4/5 293 -136 250 12 4/5 586 -133 500 12 4/5 1172 -130 4.1.1.5. lora tm transmission parameter relationship with a knowledge of the key parameters that ca n be controlled by the user we define the lora tm ? symbol rate as: rs bw 2 sf -------- - = where bw is the programmed bandwidth and sf is the spread ing factor. the transmitted si gnal is a constant envelope signal. equivalently, one chip is s ent per second per hz of bandwidth.
www.semtech.com page 27 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.1.6. lora tm packet structure the lora tm modem employs two types of packet format, explicit a nd implicit. the explicit packet includes a short header that contains information about the numb er of bytes, coding rate and whether a crc is used in the packet. the packet format is shown in the following figure. the lora tm ? packet comprises three elements: ? a preamble. ? an optional header. ? the data payload. figure 6. lora tm packet structure preamble the preamble is used to synchronize receiver with the incomi ng data flow. by default the packet is configured with a 12 symbol long sequence. this is a programmable variable so the preamble length may be extended, for example in the interest of reducing to receiver duty cycle in receive intensive applications. the transmitted preamble length may be changed by setting the registers regpreamblemsb and regpreamblelsb from 6 to 65535, yielding total preamble lengths of 6 + 4 to 65535 + 4 symbols, once the fixed overhead of the preamble data is considered. this permits the transmission of near arbitrarily long preamble sequences. the receiver undertakes a preamble detection process that periodically restarts. for this reason the preamble length sh ould be configured identical to the transmitter preamble length . where the preamble length is not known, or can vary, the maximum preamble length should be programmed on the receiver side. header depending upon the chosen mode of operation two types of he ad er are available. the header type is selected by the implictheadermodeon bit found within the regmodemconfig1 register. explicit header mode this is the default mode of operation. here the h eader provides information on the payload, namely: ? the payload length in bytes. ? the forward error correction code rate ? the presence of an optional 16-bits crc for the payload.
www.semtech.com page 28 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the header is transmitted with maximum error correction code (4/8). it also has its own crc to allow the receiver to discard invalid headers. in explicit header mode the presence of the payload crc sele cted on the transmit side through the use of the bit rxpayloadcrcon locatind in the register regmodemconfig1 . the corresponding bit (rxpayloadcrcon) is hence unused on th e receive side. instead, upon reception of the payload, may consult the bit crconpayload in the register reghopchannel. if the bit crconpayload is at ?1? then the user should then check the irq flag payloadcrcerror to ensure that the crc is valid. if the bit crconpayload is at ?0?, it me ans there w as no crc on the payload and thus the irq flag payloadcrcerror will not be trigged in the event of payload errors. explicit header transmitter receiver crc status value of the bit rxpaylo adcrcon 0 0 1 1 i mplicit header mode in certain scenarios, where the payload, coding rate and crc pre sence are fixed or known in advance, it may be advantageous to reduce transmission time by invoking implicit header mode. in this mode the header is removed from the packet. in this case the payload length, error coding rate and presence of the payload crc must be manually configured on both sides of the radio link. note that with sf = 6 selected implicit header mode is the only mode of operation possible. to avail of the payload crc in implicit header mode, it is necessar y to set the bit rxpayloadcrcon in the register regmodemconfig1 on both sides (tx and rx). implicit header transmitter receiver crc status value of the bit rxpaylo adcrcon 0 0 1 1 low data rate optimization given the potentially long duratio n of the packet at high spreading factors the option is given to improve the robustness of the transmission to variations in frequency over the dur ation of the packet transmission and reception. the bit lowdatarateoptimize increases the robustness of the lora link at these low effective data rates, its use is mandated with spreading factors of 11 and 12 at 125 khz bandwidth. 0 crc is not checked 1 crc is not checked 0 crc is checked 1 crc is checked 0 crc is not checked 1 cr c is always wrong 0 crc is not checked 1 crc is checked
www.semtech.com page 29 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation payload the packet payload is a variable-length field that contains the ac tual d ata coded at the error ra te either as specified in the header in explicit mode or in the register settings in implicit mode. an optional crc may be appended. for more information on the payload and how it is loaded from the data buffer fifo please see section 4.1.2.3 . 4.1.1.7. time on air for a given combination of spreading factor (sf), coding rate (cr) and signal bandwidth (bw) the total on-the-air tr ansmission time of a lora tm packet can be calculated as follows. from the definition of the symbol rate it is convenient to define the symbol period: ts 1 rs ----- - = the lora packet duration is the sum of the duration of the pr eamble and the transmitted packet. the preamble length is calculat ed as follows: t preamble n preamble 4.25 + ?? t sym = where n preamble is the programmed preamble length, taken from the registers regpreamblemsb and regpreamblelsb . the payload duration depends upon the header mode that is ena bled. the following formula gives the number of payload symbols. n payload 8 max ceil 8 pl 4 sf ?2816 crc 20 ih ? ++ ?? 4 sf 2 de ? ?? ---------------------------------------------------------------------------------------- cr 4+ ?? 0 ? ?? ?? += where pl is the number of bytes of payload, sf is the spreadin g factor, ih = 1 when implicit header mode is enabled and ih = 0 when explicit header mode is used. de set to 1 indicates the use of the low data rate optimization, 0 when disabled. crc indicates t he presence of the payload crc = 1 when on 0 when off. cr is the programmed coding rate from 1 to 4. the ceil fu nction indicates that the portion of the equation in square brackets should be rounded up to the next integer value. the max function compares the evaluated ceil function result and returns 0 or the result - whichever is higher. t payload n payload t s ? = addition of the preamble and payload durations gives the total packet time on air. t packet t preamble t payload + = 4.1.1.8. frequency hopping with lora tm frequency hopping spread spectrum (fhss) is typically empl oyed when the duration of a single packet could exceed regulatory requirements relating to the maximum permissible ch annel dwell time. this is mo st notably the case in us operation where the 902 to 928 mhz ism band which makes provision for frequency hopping operation. to ease the implementation of fhss systems the frequency hopping mode of the lora tm modem can be enabled by setting freqhoppingperiod to a non-zero value in register reghopperiod .
www.semtech.com page 30 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation principle of operation the principle behind the fhss sche me is that a portion of each lora tm packet is transmitted on each hopping channel from a look up table of frequencies managed by the host microcontroller. after a predetermined hopping period the transmitter and receiver change to the next channel in a pr edefined list of hopping frequencies to continue transmission and reception of the next portion of the packet. the time which the transmi ssion will dwell in any given channel is determined by freqhoppingperiod which is an integer mult iple of symbol periods: hoppingperiod s ?? ts freqhoppingperiod ? = the frequency hopping transmission and reception process star ts at channel 0. the preamble and header are transmitted first on channel 0. at the beginning of each transmission the channel counter fhsspresentchannel ( located in the register reghopchannel ) is incremented and the interrupt signal fhsschangechannel is generated. the new frequency must then be programmed within the hopping period to ensure it is taken into account for the next hop, the interrupt changechannelfhss is then to be cleared by writing a logical ?1?. fhss reception always starts on channel 0. the receiver wait s for a valid preamble detection before starting the frequency hopping process as described above. note that in the eventuality of header crc corruption, the receiver will automatically request channel 0 and recommence the valid preamble detection process. timing of channel updates the interrupt requesting the channel change, fh sschannelchange, is generated upon transition to the new frequency. the frequency hopping process is illu strated in the diagram below: figure 7. interrupts generated in the ca se of successful fr equency hopping communication.
www.semtech.com page 31 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.2. lora tm digital interface the lora tm modem comprises three types of digital interface, static configuration registers, st atus registers and a fifo data buffer. all are accessed through the sx1272/73?s spi interf ace - full details of each type of register are given below. full listings of the register addresses us ed for spi access are given in section 6.3 . 4.1.2.1. lora tm configuration registers configuration registers are accessed through the spi interface. registers are readable in all device mode including sleep. however, they should be written only in sleep and standby modes . please note that the automatic top level sequencer (tls modes) are not available in lora tm mode and the configuration register mapping changes as shown in table 39 . t he content of the lora tm configuration registers is retained in fsk/ook mode. for the functionality of mode registers common to both fsk/ook and lora tm mode, please consult the analog and rf front end section of this document (section 5 ). 4.1.2.2. status registers status registers provide status info rm ation during receiver operation. 4.1.2.3. lora tm mode fifo data buffer overview the sx1272/73 is equipped with a 256 byte ram data buffer which is uniquely accessible in lora mode. this ram area, herein referred to as the fifo data buffe r, is fully customizable by the user and a llows access to the received, or to be transmitted, data. a ll access to the lora tm fifo data buffer is done via the spi in terface. a diagram of the user defined memory mapping of the fifo data buffer is shown below. these fifo data buffer can be read in all operating modes except sleep and store data related to the last receive operat ion performed. it is automatically cleared of old content upon each new transition to receive mode. figure 8. lora tm data buffer
www.semtech.com page 32 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation principle of operation thanks to its dual port configuration, it is possible to simult aneously store both transmit and receive information in the fifo data buffer. the register regfifotxbaseaddr specifies the point in memory where the transmit inform ation is stored. similarly, for receiver operation, the register regfiforxbaseaddr indicates the point in the da ta buffer where information will be written to in event of a receive operation. by default, the device is configured at power up so th at half of the available memory is dedicated to rx ( regfiforxbaseaddr initialized at address 0x00) and the other half is dedicated for tx ( regfifotxbaseaddr initialized at address 0x80). however, due to the contiguous nature of the fifo data buffer, the base addresse s for tx and rx are fully configurable across the 256 byte memory area. each pointer can be set independently anywhere within the fifo. to exploit the maximum fifo data buffer size in tran smit or receive mode, the whole fifo data buffer can be used in each mode by setting the base addresses regfifotxbaseaddr and regfiforxbaseaddr at the bottom of the memory (0x00). the fifo data buffer is cleared when the device is put in sleep mode, consequently no access to the fi fo data buffer is possible in sleep mode. however, the data in the fifo data buffer are retained when switching across the other lora tm modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. the fifo data buffer is not self-clearing (unless if the device is put in sl eep mode) and the data will on ly be ?erase d? when a new set of data is written into the occupied memory location. the fifo data buffer location to be read from, or written to, via the spi interface is defined by the address pointer regfifoaddrptr . before any read or write operation it is hence necessa ry to initialize this pointe r to the corresponding base value. upon reading or writing to the fifo data buffer ( regfifo ) the address pointer will then increment automatically. the register regrxnbbytes defines the size of the memory location to be written in the event of a successful receive operation. the register regpayloadlength indicates the size of the memory location to be transmitted. in implicit header mode, the register regrxnbbytes is not used as the number of payload bytes is known. otherwise, in explicit header mode, the initial size of the receive buffer is set to the packet length in the received header. the register regfiforxcurrentaddr indicates the location of the last packet received in the fifo so that the last packet received can be easily read by pointing the register regfifoaddrptr to this register. it is important to note that all the receiv ed data will be written to th e fifo data buffer even if the crc is invalid, permitti ng user defined post processing of corrupted da ta. it is also important to note that when receiving, if the packet size exceeds the buffer memory allocated for t he rx, it will overwrite the transm it portion of the data buffer. 4.1.2.4. interrupts in lora mode two registers are used to control the interrupt signa ls (irq) available in lora mode: the register regirqflags contains the state of the interrupts themselves and the register regirqflagsmask which can be used to mask the interrupts. the interrupt mask regirqflagsmask, allows the user to mask indi vidual interrupts, in this case setting a bit to ?1? will mask - so deactivate the interrupt at the same position in the regirqflags register. by default all the interrupts are unmasked, so available. in the register regirqflags , a ?1? indicates a given irq has been trigged and then the irq must be clear by writing a ?1?.
www.semtech.com page 33 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.3. operation of the lora tm modem 4.1.3.1. operating mode control the operating modes of the lora tm modem are accessed by enabling lora tm mode (setting the longrangemode bit of regopmode ). depending upon the operating mode selected the rang e of functionality and register access is given by the following table: table 15 lora tm ? it is possible to access any mode from any other mode by changing the value in the regopmode register. operating mode description sleep low-power mode. in this mode only spi and configuration registers are accessible. lora fifo is not accessible. note that this is the only mode permissi ble to switch between fsk/ook mode and lora mode. standby both crystal oscillator and lora baseband blocks are turned on. rf front-end and plls are disabled fstx this is a frequency synthesis mode for transmission. the pll selected for transmission is locked and active at the transmit frequency. the rf front-end is off. fsrx this is a frequency synthesis mode for reception. the pl l selected for reception is locked and active at the receive frequency. the rf front-end is off. tx when activated the sx1272/73 powers all remaining blocks required for transmit, ramps the pa, transmits the packet and returns to standby mode. rxcontinuous when activated the sx1272/73 powers all remaining blo cks required for reception, processing all received data until a new user request is made to change operating mode. rxsingle when activated the sx1272/73 powers all remaining blocks required for reception, remains in this state until a valid packet has been received and then returns to standby mode. cad when in cad mode, the device will check a given channel to detect lora preamble signal
www.semtech.com page 34 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.4. frequency settings recalling that the freque ncy step is given by: f step f xosc 2 19 ---------------- = in order to set lo frequency values following registers are available. frf is a 24-bit register which defines carrier frequency. the ca rr ier frequency relates to the register contents by following formula: f rf f step frf 23 0 (,) ? = 4.1.5. frequency error indication the sx1272 derives its rf centre frequency from a crystal re ference oscillator which has a finite frequency precision. errors in reference frequency will manifest themselves as errors of the same proportion from the rf centre frequency. in lora receive mode the sx1272 is capable of measuring the fre quency offset between the receiver centre frequency and that of an incoming lora signal. the image below shows the estimated frequency offset and corresponding per for various coding rates as a function of frequency offset. here we can see that the modem is intolerant of frequency offsets in the region of +/- 20% of the bandwidth and will accurately re port the error over this same range. figure 9. applied versus measur ed frequency offset and influence on per. the error is read by reading the three regfei registers. the contents of which ar e a signed 20 bit two's compliment word, freqerror . the frequency error is determined from the register contents by: f error freqerror 2 24 ? f xtal ----------------------------------------- - = where fxtal is the crystal frequency. please note that the measured fei should not be applied to the rf centre frequency to perform afc. the fei m easurement is provided for information only.
www.semtech.com page 35 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.1.6. lora tm modem state machine sequences the sequence for transmission and reception of data to and from the lora tm modem, together with flow charts of typical sequences of operation, are detailed below. data transmission sequence in transmit mode power consumption is optimized by enabling rf , pll and pa blocks only when packet data needs to be transmitted. figure 10 shows a typical lora tm ?? transmit sequence. figure 10. lora tm modulation transmission sequence. ? static configuration registers can only be acce ssed in sleep mode, standby mode or fstx mode. ? the lora tm fifo should only be fille d in standby mode and canno t be filled in sleep mode. ? data transmission is initiated by sending tx mode request. ? upon completion the txdone interrupt is issued and the radio returns to standby mode. ? following transmission the radio can be manually placed in sleep mode or the fifo refilled for a subsequent tx operation.
www.semtech.com page 36 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation lora tm ? transmit data fifo filling in order to write packet data into fifo user should: 1set fifoad drptr to fifotxbaseaddrs . 2write payloadlength bytes to the fifo ( regfifo ) data reception sequence figure 11 shows typical lora tm receive sequences for both single and continuous receiver modes of operation. figure 11. lora tm receive sequence.
www.semtech.com page 37 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the lora tm modem can work in two distinct reception modes: 1. single receive mode 2. continuous receive mode single reception operating mode in this mode, the modem searches for a preamble during a given period of time. if a preamble hasn?t been found at the end of the time window, the chip generates the rxtimeout interrupt and goes back to standby mode. the length of the reception window (in symbols) is defined by the regsymbtimeout register and should be in the range of 4 (minimum time for the modem to acquire lock on a preamble) up to 1023 symbols. at the end of the payload, the rxdone interrupt is generated together with the interrupt payloadcrcerror if the payload crc is not valid. however, even when the cr c is not valid, the data are written in the fifo data buffer for post processing. following the rxdone interrupt the radio goes to standby mode. the modem will also automatically return in standby mode when the interrupts rxdone is generated. therefore, this mode should only be used when the time window of arrival of the pa cket is known. in other cases, the rx continuous mode should be used. in rx single mode low-power is achieved by turning off pll and rf blocks as soon as a packet has been received. the flow is as follows: 1 set fifoaddrptr to fiforxbaseaddr . 2 static configuration register device can be writ ten in either sleep mode, standby mode or fsrx mode. 3 a single packet receive o peration is initiated by select ing the operating mode rxsingle. 4 the receiver will then await the recept ion of a valid preamble. once received, the gain of the receive chain is set. following the ensuing reception of a valid header, indicated by the validheader interrupt in explicit mode. the packet reception process commences. once the reception process is complete the rxdone interrupt is set. the radio then returns automatically to standby mode to reduce power consumption. 5 the receiver status register payloadcrcerror should be checked for packet payload integrity. 6 if a valid packet payload has been received then the fifo should be read (see payload data extraction below). should a subsequent single packet reception need to be triggered, then the rxsingle operating mode must be re-selected to launch the receive process again - taking care to reset the spi pointer ( fifoaddrptr ) to the base location in memory ( fiforxbaseaddr ). continuous reception operating mode in continuous receive mode, the modem scans the channel cont inuously for a preamble. each time a preamble is detected the modem tracks it until the packet is received and then carries on waiting for the next preamble. if the preamble length exceeds the anticipated value set by the registers regpreamblemsb and regpreamblelsb (measured in symbol periods) the preamble will be dropped and the search for a preamb le restarted. however, th is scenario will not be flagged by any interrupt. in continuous rx mode, opposite to the single rx mode , the rxtimeout inte rrupt will never occur and the device will ne ver go in standby mode automatically. it is also important to note that the demodulated bytes are wri tten in the data buffer memory in the order received. meaning, the first byte of a new packet is written just after the last byte of the preceding packet. the rx modem address pointer is never reset as long as this mode is enabled. it is therefore necessary for the companion microcontroller controller to handle the address pointer to make sure th e fifo data buffer is never full.
www.semtech.com page 38 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation in continuous mode the received packet processing sequence is given below. 1 whilst in sleep or standby mode select rxcont mode. 2 upon reception of a valid header crc the rxdone i nterrupt is set. the radio remains in rxcont mode waiting for the next rx lora tm ? packet. 3 the payloadcrcerror flag should be checked for packet integrity. 4 if packet has been correctly received the fifo data buffer can be read (see below). 5 the reception process (steps 2 - 4) can be repeated or receiver operating mode exited as desired. in continuous mode status information are available only fo r the last packet received, i.e. the corresponding registers should be read before the next rxdone arrives. rx single and rx continuous use cases the lora single reception mode is used mainly in battery operated systems or in systems where the companion microcontroller has a limited availability of timers. in such systems, t he use of the timeout present in rx single reception mode allows the end user to limit the amount of time spent in reception (and thus limiting t he power consumption) while not using any of the companion mcu timers (the mcu can then be in sleep mode while the radio is in the reception mode). the rxtimeout interrupt generated at the end of the reception period is then used to wake-up the companion mcu. one of the advantages of the rxsingle mode is that the interrupt rxtimeout will not be triggered if the device is currently receiving data, thus giving the priority to the reception of the data over the timeout. however, if during the reception, the device lose s track of the data due to external perturbation, the device will drop the reception, flag t he interrupt rxtimeout and go in standby mode to decrease the power consumption of the system. on the other hand, the lora continuous reception mode is used in systems which do not have power restrictions or on system where the use of a companion mcu timer is preferred over the radio embedded timeou t system. in rxcontinuous mode, the radio will track any lora signal present in the air and carry on the reception of packets until the companion mcu sets the radio into another mode of operation. upon reception the interrupt rxdone will be trigged but the device will stay in rx mode, ready for the reception of the next packet. payload data extraction from fifo in order to retrieve received data from fifo the user must ensure that validheader , payloadcrcerror, rxdone and rxtimeout interrupts in the status register regirqflags are not asserted to ensure that packet reception has terminated successfully (i.e. no flags should be set). in case of errors the steps below should be skipped and the packet discarded. in order to retrieve valid received data from the fifo the user must: ? regrxnbbytes indicates the number of bytes that have been received thus far. ? regfifoaddr ptr is a dynamic pointer that indicates precisely w here the lora modem received data has been written up to. ? set regfifoaddr ptr to regfiforxcurrentaddr . this sets the fifo pointer to the location of the last packet received in the fifo. the payload can then be extracted by reading the register regfifo, regrxnbbytes times. alternatively, it is possible to manually point to the locati on of the last packet received, from the start of the current packet, by setting regfifoaddrptr to regfiforxbyteaddr minus regrxnbbytes . the payload bytes can then be read from the fifo by reading the regfifo address regrxnbbytes times.
www.semtech.com page 39 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation packet filtering based on preamble start the lora tm modem does not automatically filter received packets based upon an address. however, the sx1272/73 permits software filtering of the received packets based on the contents of the first few bytes of payload. a brief example is given below for a 4 byte address, however, the ad dress length can be selected by the designer. the objective of the packet filtering process is to determine th e presence, or otherwise, of a valid packet designed for the receiver. if the packet is not for the re ceiver then the radio returns to sleep mo de in order to improve battery life.the software packet filtering pr ocess follows the steps below: ? each time the rxdone interrupt is received, latch th e regfiforxbyteaddr[7:0] register content in a variable, this variable will be calle d start_address. the regfiforxbyteaddr[7:0] register of the sx1272 gives in real time the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be wr itten by the receive lora tm modem). so by doing this, we make sure that the variable st art_address always contains the start address of the next packet. ? upon reception of the interrup t validheader, start polling the regfiforxbyteaddr[7:0] register until it begins to increment. the speed at which this regi ster will increment depends on the spreadin g factor, the error correction code and the modulation bandwi dth. (note that this interrupt is st ill generated in im plicit mode). ? as soon as regfiforxbyteaddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the fifo data buffer. these can be read and tested to see if the packet is destined for the radio and either remaining in rx mode to receive the packet or returning to sleep mode if not. receiver timeout operation in lora tm rx single mode, a receiver timeout functionality is available that pe rmits the receiver to listen for a predetermined period of time before generating an interrupt signal to indicate that no valid packets have been received. the timer is absolute and commences as soon as the radio is placed in single receive mode. the interrupt itself, rxtimeout , can be found in the interrupt register regirqflags . in rx single mode, the device will re turn to standby mode as soon as the interrupt occurs. the user must then clear the interrupt or go into sleep mode before returning into rx single mode. the programmed timeout value is expressed as a mu ltiple of the symbol period and is given by: timeout lorarxtimeout ts ? =
www.semtech.com page 40 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation channel activity detection the use of a spread spectrum modulation technique presents c hallenges in determining whether the channel is already in use by a signal that may be below the noise floor of the receiver. the use of the r ssi in this situation would clearly be impracticable. to this end the channel activity de tector is used to dete ct the presence of other lora tm signals. figure 12 shows the channel activity detection (cad) process: figure 12. lora tm cad flow
www.semtech.com page 41 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation principle of operation the channel activity detection mode is designed to detect a lora preamble on the radio channel with the best possible power efficiency. once in cad mode, the sx1272/73 will perform a very quick scan of the band to detect a lora tm packet preamble. during a cad the following operations take place: ? the pll locks ? the radio receiver captures lora tm preamble symbol of data from the channel. the radio current consumption during that phase is approximately 10 ma. ? the radio receiver and the pll turn off and the modem digital processing starts. ? the modem searches for a correlation between the radio ca ptured samples and the idea l preamble waveform. this correlation process takes a little bit less than a symbol period to perform. the radio current consumption during that phase is greatly reduced. ? once the calculation is finished the modem generates the caddone interrupt. if the correlation was successful, the caddetected is generated simultaneously. ? the chip goes back to standby mode. ? if a preamble was detected, clear the interrupt, then initiate the reception by putting the radio in rx single mode or rx continuous mode. the time taken for the channel activi ty detection is dependent upon the lora tm modulation settings used. for a given configuration the typical cad detection time is shown in the graph below, expressed as a multiple of the lora tm symbol period. of this period the radio is in receiver mode for (2 sf + 32) / bw seconds. for the remainder of the cad cycle the radio is in a reduced consumption state. figure 13. channel activity detection (cad) time as a function of spreading factor.
www.semtech.com page 42 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation to illustrate this process and the respec tive consumption in each mode, the cad process follows the sequence of events outlined below: figure 14. consumption profile of the lora cad process the receiver is then in full receiver mode for just over half of the activity detection, fo llowed by a reduced consumption processing phase where the consumption varies with the lora bandwidth as shown in the table below. table 16 bandwidth (khz) full rx, iddr_l (ma) processing, iddc_l (ma) 125 10.8 5.6 250 11.6 6.5 500 13 8 lora cad consumption figures 4.1.6.1. digital io pin mapping six of sx1272/73?s general purpose io pins are available used in lo ra tm mode. their mapping is shown below and depends upon the configuration of registers regdiomapping1 and regdiomapping2. table 17 operating mode diox mapping dio5 dio4 dio3 dio2 dio1 dio0 all 00 modeready caddetected caddone fhsschangechannel rxtimeout rxdone 01 clkout plllock validheader fhsschangechannel fhsschangechannel txdone 10 clkout plllock payloadcrcerror fhsschangechannel caddetected caddone 11 - - - - - - dio mapping lora tm mode
www.semtech.com page 43 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2. fsk/ook modem 4.2.1. bit rate setting the bit rate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalen tly chip) rate of the radio. in continuous transmit mode (section 4.2.13 ) the data stream to be transmitted can be input directly to the modulator via pin 9 (dio2/data) asynchronously, unless g aussian filtering is used, in which case the dclk signal on pin 10 (dio1/dclk) is used to clock-in the data stream. see section 4.2.2.3 for details of the gaussian filter. in packet mode or in continuous mode with gaussian filt er ing enabled, the bit rate (br) is controlled by bits bitrate in regbitratemsb and regbitratelsb bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- = note: bitratefrac bits have no effect (i.e may be considered equal to 0) in ook modulation mode. the quantity bitr atefrac is hence designed to allow very high precision (max. 250 ppm programing resolution) for any bitrate in the programmable range. ta b l e 18 below shows a range of standard bitrat es an d the accuracy to within which they may be attained. table 18 bit rate examples type bitrate (15:8) bitrate (7:0) (g)fsk (g)msk ook actual br (b/s) classical modem baud rates (multiples of 1.2 kbps) 0x68 0x2b 1.2 kbps 1.2 kbps 1200.015 0x34 0x15 2.4 kbps 2.4 kbps 2400.060 0x1a 0x0b 4.8 kbps 4.8 kbps 4799.760 0x0d 0x05 9.6 kbps 9.6 kbps 9600.960 0x06 0x83 19.2 kbps 19.2 kbps 19196.16 0x03 0x41 38.4 kbps 38415.36 0x01 0xa1 76.8 kbps 76738.60 0x00 0xd0 153.6 kbps 153846.1 classical modem baud rates (mu ltiples of 0.9 kbps) 0x02 0x2c 57.6 kbps 57553.95 0x01 0x16 115.2 kbps 115107.9
www.semtech.com page 44 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.2. fsk/ook transmission 4.2.2.1. fsk modulation fsk modulation is performed inside the pll bandwidth by changi n g the fractional divider ratio in the feedback loop of the pll. the high resolution of the sigma-delta modulator allows for very narrow frequency devi ation. the frequency deviation f dev is given by: f dev f step fdev 13 0 (,) ? = to ensure correct modulation the following limit applies: f dev br 2 ------- 250 ?? khz ? + note no constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between 600 hz and 200 khz. 4.2.2.2. ook modulation ook modulation is applied by switching on and off the power amp lifier . digital control and ramp ing are available to improve the transient power response of the ook transmitter. 4.2.2.3. modulation shaping modulation shaping can be applied in both ook and fsk modulation modes to improve the narrowband response of the tr ansmitter. both shaping features are controlled with paramp bits in regparamp. ? in fsk mode, a gaussian filter with bt = 0.5 or 1 can be used to filter the modulation stre am, at the input of the sigma- delta modulator. if the gaussian filter is enabled when the sx1272/73 is in continuous mode, dclk signal on pin 10 (dio1/dclk) will trigger an inte rrupt on the uc each time a new bit has to be transmitted. pl ease refer to section 4.2.13.2 for details. ? when ook modulation is used the pa bias voltages are ramped up and down smoothly when the pa is turned on and off to reduce spectral splatter. round bit rates (multiples of 12.5, 25 and 50 kbps) 0x0a 0x00 12.5 kbps 12.5 kbps 12500.00 0x05 0x00 25 kbps 25 kbps 25000.00 0x80 0x00 50 kbps 50000.00 0x01 0x40 100 kbps 100000.0 0x00 0xd5 150 kbps 150234.7 0x00 0xa0 200 kbps 200000.0 0x00 0x80 250 kbps 250000.0 0x00 0x6b 300 kbps 299065.4 watch xtal frequency 0x03 0xd1 32.768 kbps 32.768 kbps 32753.32 type bitrate (15:8) bitrate (7:0) (g)fsk (g)msk ook actual br (b/s)
www.semtech.com page 45 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation note the transmitter must be restarted if the modulationshapi ng setting is changed in order to recalibrate the built-in filte r. 4.2.3. fsk/ook reception 4.2.3.1. fsk demodulator the fsk demodulator of the sx1272/73 is designed to demodul ate fs k, gfsk, msk and gmsk modulated signals. it is most efficient when the modulation index ( ) of the signal is greater than 0.5 and below 10: 0.5 ?? 2 f dev ? br ---------------------- 10 ? = the output of the fsk demodulator can be fed to the bit synchronizer to provide the companion processor with a synchronous data stream in continuous mode. 4.2.3.2. ook demodulator the ook demodulator performs a comparison of the rssi outpu t and a threshold value. three different threshold modes are available, configured through bits ookthreshtype in regookpeak . the recommended mo de of operation is the ?peak? threshold mode, illustrated in figure 15: zoom period as defined in ookpeakthreshdec decay in db as defined in ookpeakthreshstep fixed 6db difference rssi [dbm] noise floor of receiver ??floor?? threshold defined by ookfixedthresh time ??peak -6db?? threshold zoom figure 15. ook peak demodulator description in peak threshold mode the comparison threshold level is the peak value of the rssi reduce d by 6 db. in the absence of an input signal, or during the reception of a logical ?0?, the acquired peak value is decremented by one ookpeakthreshstep every ookpeakthreshdec period. when the rssi output is null for a long time (for instance after a lo ng string of ?0? received or if no transmitter is present) the peak threshold level will continue falling until it reaches the ?floor threshold? programmed in ookfixedthresh .
www.semtech.com page 46 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the default settings of the ook demodulator lead to the perfor mance stated in the electrical specification. however, in applications in which sudden received si gnal power reduction is possible, the three parameters should be optimized accordingly. optimizing the floor threshold ookfixedthresh de termines the sensitivity of the ook receiver, as it sets the comparison thres hold for weak input signals (i.e. those close to the noise floor). significant sensitiv ity improvements can be gener ated if configured correctly. note that the noise floor of the receiver at the demodulator input depends on: ? the noise figure of the receiver. ? the gain of the receive chain from antenna to base band. ? the matching - includin g saw filter if any. ? the bandwidth of the channel filters. it is therefore important to note that the setting of o okfixedthresh will be application dependa nt. the followi ng procedure is recommended to optimize ookfixedthresh . set sx1272/3 in ook rx mode adjust bit rate, channel filter bw default ookfixedthresh setting no input signal continuous mode optimization complete glitch activity on data ? monitor dio2/data pin increment ookfixedthresh figure 16. floor threshold optimization the new floor threshold value found during this test should be used for ook reception wi th those receiver settings. optimizing ook demodulator for fast fading signals a sudden drop in signal strength can cause the bit error rate to increase. for applications where the expected signal drop can be estimated, the following ook demodulator parameters ookpeakthreshstep and ookpeakthreshdec can be optimized as described below for a given number of threshold decrements per bit. refer to regookpeak to access those settings.
www.semtech.com page 47 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation alternative ook demodulator threshold modes in addition to the peak ook threshold mode, the user can alternatively select two other types of threshold detectors: ? fixed threshold: the value is selected through ookfixedthresh ? average threshold: data supplied by the rssi block is av eraged (this operation mode should only be used with dc- free encoded data). 4.2.3.3. bit synchronizer the bit synchronizer provides a clean and synchr onized digital output based upo n timing recovery information gleaned from the received data edge transitions. its output is made available on pin dio1/dclk in continuous mode and can be disabled through register settings. however, for optimum receiv er performance, especially in continuous receive mode, its use is strongly advised. the bit synchronizer is automatically activated in pack et mode. its bit rate is controlled by bitratemsb and bitratelsb in regbitrate. raw demodulator output (fsk or ook) dclk data bitsync output to pin data and dclk in continuous mode figure 17. bit synchronizer description to ensure correct operation of the bit synchronizer the following conditions have to be satisfied: ? a preamble (0x55 or 0xaa) of at least 12 bits is required fo r synchronization, the longer the synchronization phase is the better the ensuing packet detection rate will be. ? the subsequent paylo ad bit stream must have at least one edge transition (eit her rising or falling) every 16 bits during data transmission. ? the absolute error between transmitted and received bit rate must not exceed 6.5%.
www.semtech.com page 48 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.3.4. frequency error indicator this frequency error indicator measures the frequency error between the programmed rf centre frequency and the carrier frequency of the modulated input signal to the receiver. when the fei is performed the frequency error is measured and the signed result is loaded in feivalue in regfei in 2?s complement format. the time required for an fei evaluation is 4 bit periods. to ensure correct operation of the fei: ? the measurement must be launched during the reception of preamble. ? the sum of the frequency offset and the 20 db signal bandwidth must be lower than the base band filter bandwidth. i.e. the whole modulated spectrum must be received. the 20 db bandwidth of the signal can be evaluated as follows (double-side bandwidth): bw 20 db 2 f dev br 2 ------- + ?? ?? ? = the frequency error, in hz, can be calculated with the following formula: fei f step feivalue ? = the fei is enabled automatically upon the transition to receive mode and automatically updated every 4 bits. 4.2.3.5. afc the afc is based on the fei measurement therefore the same in put signal and receiver setting conditions apply. when the afc procedure is performed the afcvalue is directly subtracted from the regi ster that defines the frequency of operation of the chip, f rf . the afc is executed each time the receiver is enabled, if afcautoon = 1. when the afc is enabled ( afcautoon = 1 ) the user has the option to: ? clear the former afc correction value if afcautoclearon = 1. allowing the next frequency correction to be performed from the initial centre frequency. ? start the afc evaluation from the previously corrected frequen cy. this may be useful in systems in which the centre frequency experiences cumulative drift - such as the ageing of a crystal reference. the sx1272/73 offers an alternate receiver bandwidth settin g d uring the afc phase allowing the accommodation of larger frequency errors. the setting regafcbw sets the receive bandwidth during the afc process. in a typical receiver application, once the afc is performed, the radio will revert to the receiver communication or channel bandwidth ( regrxbw ) for the ensuing communication phase. note that the fei measurement is valid only during the reception of preamble. the provision of the preambl edetect flag can hence be used to detect this condition and allow a reliable afc or fei operation to be triggered. this process can be performed automatically by using the appropriate options in startdemodonpreamble found in the regrxconfig register. a detailed description of the receiver setup to enable the afc is provided in section 4.2.7 .
www.semtech.com page 49 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.3.6. preamble detector the preamble detector indicates the reception of a carrier modulated with a 0101...sequence. it is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. the size of detection can be programmed from 1 to 3 bytes with preambledetectorsize in regpreambledetect as defined in the next table. table 19 preamble detector settings for normal operation, preambledetecttol should be set to be set to 10 (0x0a) with a qualifying preamble size of 2 bytes. the preambledetect interrupt (either in regirqflags1 or mapped to a specific dio) then goes high every time a valid preamble is detected assuming preambledetectoron =1. the preamble detector can also be used as a gate to ensure that afc and agc are performed on valid preamble. see section 4.2.7 . for details. 4.2.3.7. image rejection mixer the sx1272/73 employs an image rejection mixer (irm) which, uncalibrated, gives 35 db image rejection. the low phase noise pll is used to perform calibration of the receiver chai n. which increases the typical im age rejection to 48 db. this process is fully automated in fsk/ook mode and radio power-up. 4.2.3.8. image and rssi calibration an automatic calibration process is used to calibrate the phas e and gain of both i and q receive paths. this calibration allows enhanced image frequency rejection and improves the rssi precision. this calibration process is launched under the following circumstances: ? automatically at power on reset or after a manual reset of the chip (refer to section 7.2). for applications where the temperature remains stable, or if the image rejection is not a major concern, this single calibration will suffice. ? automatically when a pre-defined temperature change is observed. ? upon user request, by setting bit imagecalstart in regimagecal , when the device is in st andby mode. note that in lora tm mode the calibration command is inaccessible. to perform the calibration the radio must be returned temporarily to fsk/ook mode. a selectable temperature change, set with tempthreshold (5, 10, 15 or 20c), is detected and reported in tempchange if the temperature monitoring is turned on with tempmonitoroff = 0 . this interrupt flag can be used by the application to launch a new image calibration at a convenient time if autoimagecalon =0, or immediately when this temp erature variation is detected, if autoimagecalon =1. preambledetectorsize # of bytes 00 1 01 2 (recommended) 10 3 11 reserved
www.semtech.com page 50 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the calibration process takes approximately 10 ms. 4.2.3.9. timeout function the sx1272/73 includes a timeout function, which allows the autom ation of a duty-cycled re cceive oprtation where the radio periodically wakes from sleep mode into receiver mode. ? timeout interrupt is generated timeoutrxrssi x 16 x tbit after switching to rx mode if the rssi flag does not raise within this time frame ( rssivalue > rssithreshold ). ? timeout interrupt is generated timeoutrxpreamble x 16 x tbit after switching to rx mode if the preambledetect flag does not raise within this time frame. ? timeout interrupt is generated timeoutsignalsync x 16 x tbit after switching to rx mode if the syncaddress flag does not raise within this time frame. this timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power m ode. to become active, these timeouts must also be enabled by setting the correct rxtrigger parameters in regrxconfig: table 20 rxtrigger settings to enable timeout interrupts receiver triggering event rxtrigger (2:0) timeout on rssi timeout on preamble timeout on syncaddress 4.2.4. operating modes in fsk/ook mode 4.2.5. general overview the sx1272/73 has several working modes, manually programmed in regopmode . fully automated mode selection, packet transmission and reception is also possible using the top level sequencer described in section 4.2.9 . table 21 basic transceiver modes when switching from a mode to another the sub-blocks ar e woken up according to a pr e-defined optimized sequence. none 000 off off active rssi interrupt 001 active off preambledetect 110 off active rssi interrupt & preambledetect 111 active active mode selected mode symbol enabled blocks 000 sleep mode sleep none 001 standby mode stdby top regulator and crystal oscillator 010 frequency synthesiser to tx frequency fstx frequency synthesizer at tx frequency (frf) 011 transmit mode tx frequency synthesizer and transmitter 100 frequency synthesiser to rx frequency fsrx frequency synthesizer at frequency for reception (frf-if) 101 receive mode rx frequency synthesizer and receiver
www.semtech.com page 51 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.6. startup times the startup time of the transmitter or the receiver is dependen t upon which mode the transceiver was in at the beginning. for a complete description, figure 18 below shows a complete startup process, from the lower power mode ?sleep?. sleep mode transmit stdby mode fstx fsrx receive timeline 0 ts_osc ts_osc +ts_fs ts_osc +ts_fs +ts_tr ts_osc +ts_fs +ts_re current drain iddsl iddst iddfs iddr (rx) or iddt (tx) figure 18. startup process ts_osc is the startup time of the crystal oscillator which depends on t he electrical characteristics of the crystal. ts_fs is the startup time of the pll including systematic calibration of the vco. typical values of ts_osc and ts_fs are given in section 2.5.2 . 4.2.6.1. transmitter startup time the transmitter startup time, ts_tr, is c alculated as follows in fsk mode: , where paramp is the ramp-up time programmed in regparamp and tbit is the bit time. in ook mode, this equation can be s implified to the following: tbitstrts ??? 2 1 5_ ? 4.2.6.2. receiver startup time the receiver startup time, ts_re, only depends upon the receiver bandwid th effective at the ti me of startup. when afc is enabled ( afcautoon =1) the afcbw should be used instead of rxbw to extract the receiver startup time: tbit paramp strts ????? 2 1 25.15_ ?
www.semtech.com page 52 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation table 22 receiver startup time summary rxbw if afcautoon=0 rxbwafc if afcautoon=1 ts_re (+/-5%) ts_re or later after setting the devic e in receive mode, any incoming packet will be detected and demodulated by the transceiver. 4.2.6.3. time to rssi evaluation the first rssi sample will be available ts_rssi after the r eceiver is ready: equivalently ts_re + ts_rssi after the receive mode instruction was issued. fsrx rx rssi irq rssi sample ready timeline 0t s _ r e t s _ r e +ts_rssi figure 19. time to rssi sample ts_rssi depends on the receiver bandwidth as well as the rssismoothing option that was selected. the formula used to calculate ts_rssi is provided in section 5.5.4 . 2.6 khz 2.33 ms 3.1 khz 1.94 ms 3.9 khz 1.56 ms 5.2 khz 1.18 ms 6.3 khz 984 us 7.8 khz 791 us 10.4 khz 601 us 12.5 khz 504 us 15.6 khz 407 us 20.8 khz 313 us 25.0 khz 264 us 31.3 khz 215 us 41.7 khz 169 us 50.0 khz 144 us 62.5 khz 119 us 83.3 khz 97 us 100.0 khz 84 us 125.0 khz 71 us 166.7 khz 85 us 200.0 khz 74 us 250.0 khz 63 us
www.semtech.com page 53 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.6.4. tx to rx turnaround time tx mode 1. set new frf (*) 2. set rx mode timeline 0t s _ h o p +ts_re (*) optional rx mode figure 20. tx to rx turnaround note the spi instruction times are omitted, as they can gener ally be very small as compared to other timings (up to 10 mhz spi clock). 4.2.6.5. rx to tx rx mode 1. set new frf (*) 2. set tx mode timeline 0t s _ h o p +ts_tr (*) optional tx mode figure 21. rx to tx turnaround
www.semtech.com page 54 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.6.6. receiver hopping, rx to rx two methods are possible: rx mode, channel a 1. set new frf 2. set restartrxwithplllock timeline 0t s _ h o p +ts_re rx mode, channel b first method rx mode, channel a 1. set fasthopon =1 2. set new frf (*) 3. wait for ts_hop timeline 0 ~ts_hop rx mode, channel b second method (*) regfrflsb must be written to trigger a frequency change figure 22. receiver hopping the second method is quicker and should be used if a very quick rf sniffing mechanism is to be implemented. 4.2.6.7. tx to tx 1. set new frf (*) 2. set fstx mode fstx timeline ~ paramp +ts_hop ~paramp +ts_hop +ts_tr 0 tx mode, channel a tx mode, channel b set tx mode figure 23. transmitter hopping 4.2.7. receiver startup options the sx1272/73 receiver can automatically control the gain of the receive chain (agc) and adjust the receiver lo frequency (afc). those processes are carried out on a packet-by-packet basis. they occur: ? when the receiver is turned on. ? when the receiver is restarted upon user request, through the use of trigger bits restartrxwithoutplllock or restartrxwithplllock in regrxconfig. ? when the receiver is automatically re started after the reception of a valid packet or after a packet collision.
www.semtech.com page 55 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation automatic restart capabilitie s are detailed in section 4.2.8 . the receiver startup options available in sx1272/73 are described in ta b l e 23 . table 23 receiver startup options triggering event realized function agcautoon afcautoon rxtrigger (2:0) when agcautoon =0, the lna gain is manually selected by choosing lnagain bits in reglna. 4.2.8. receiver restart methods the options for restart of the receiver are covered below. this is typically of use to prepare for the reception of a new signa l whose strength or carrier frequency is different from the pr eceding packet to allow the agc or afc to be re-evaluated. 4.2.8.1. restart upon user request in receive mode the user can request a receiver restart - th is can be useful in conjunction with the use of a timeout interrupt following a period of inactivity in the channel of in terest. two options are available: ? no change in the local oscillator upon restart: the afc is disabled, and the frf register has not been changed through spi before the restart instruction: set bit restartrxwithoutplllock in regrxconfig to 1. ? local oscillator change upon restart: if afc is enabled ( afcautoon =1), and/or the frf register had been changed during the last rx period: set bit restartrxwithplllock in regrxconfig to 1. note modeready must be at logic level 1 for a new restartrx command to be taken into account. 4.2.8.2. automatic restart af ter valid pack et reception the bits a utorestartrxmode in regsyncconfig control the automatic restart feature of the sx1272/73 receiver, when a valid packet has been received: ? if autorestartrxmode = 00 , the function is off, and the user should ma nually restart the receiver upon valid packet reception (see section 4.2.8.1 ). ? if autorestartrxmode = 01 , after the user has empt ied the fifo following a payloadready interrupt, the receiver will automatically restart itself after a delay of interpacketrxdelay , allowing for the distant transmitter to ramp down, hence avoiding a false rssi detection on the ?tail? of the previous packet. ? if autorestartrxmode = 10 should be used if the next reception is expected on a new frequency, i.e. frf is changed after the reception of the previous packet. an additional delay is systematically added, in order for the pll to lock at a new frequency. none none 0 0 000 rssi interrupt agc 1 0 001 agc & afc 1 1 001 preambledetect agc 1 0 110 agc & afc 1 1 110 rssi interrupt & preambledetect agc 1 0 111 agc & afc 1 1 111
www.semtech.com page 56 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.8.3. automatic restart when packet collision is detected in receive mode the sx1272/73 is able to detect packet collision and restart t he receiver. collisions are detected by a sudden rise in received signal strength, de tected by the rssi. this functionality c an be useful in network configurations where many asynchronous slaves attempt periodic communication with a single a master node. the collision detector is enabled by setting bit restartrxoncollision to 1. the decision to restart the receiver is based on the detection of rssi change. the sensitivity of the system can be adjusted in 1 db steps by using register rssicollisionthreshold in regrxconfig . 4.2.9. top level sequencer depending on the application it may be desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial inte rface. in order to define different se quences or scenarios a user-programmable state machine called the top level sequencer (herein reffered to as the sequencer) can aut omatically control the chip modes. note that this functionality is only available in fsk/ook mode. the sequencer is activated by setting the sequencerstart bit in regseqconfig1 to 1 in sleep or standby mode (called initial mode). it is also possible to force the sequencer off by setting the stop bit in regseqconfig1 to 1 at any time. note sequencerstart and stop bit must never be set at the same time. 4.2.9.1. sequencer states as shown in the table below, with the aid of a pair of interrupt timers (t1 and t2), the sequencer can take control of the chip operation in all modes. table 24 sequencer states sequencer state description sequenceroff state the sequencer is not activated. sending a sequencerstart command will launch it. when coming from lowpowerselection state, the sequencer will be off, whilst the chip will return to its initial mode (either sleep or standby mode). idle state the chip is in low- power mode, either standby or sleep , as defined by idlemode in regseqconfig1 . the sequencer waits only for the t1 interrupt. transmit state the transmitter in on. receive state the receiver in on. packetreceived the receiver is on and a packet has been received. it is stored in the fifo. lowpowerselection selects low power state ( sequenceroff or idle state)
www.semtech.com page 57 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.9.2. sequencer transitions the transitions between sequencer states are listed in the forthcoming table. table 25 sequencer transition options rxtimeout defines the action to be taken on a rxtimeout interrupt. rxtimeout interrupt can be a timeoutrxrssi , timeoutrxpreamble or timeoutsignalsync interrupt. variable transition idlemode selects the chip mode during idle state: 0: standby mode 1: sleep mode fromstart controls the sequencer transition when the sequencerstart bit is set to 1 in sleep or standby mode: 00: to lowpowerselection 01: to receive state 10: to transmit state 11: to transmit state on a fifothreshold interrupt lowpowerselection selects sequencer lowpower state after a to lowpowerselection transition 0: sequenceroff state with chip on initial mode 1: idle state with chip on standby or sleep mode depending on idlemode note: initial mode is the chip lowpower mode at sequencer start. fromidle controls the sequencer transition from the idle state on a t1 interrupt: 0: to transmit state 1: to receive state fromtransmit controls the sequencer transition from the transmit state: 0: to lowpowerselection on a packetsent interrupt 1: to receive state on a packetsent interrupt fromreceive controls the sequencer transition from the receive state: 000 and 111: unused 001: to packetreceived state on a payloadready interrupt 010: to lowpowerselection on a payloadready interrupt 011: to packetreceived state on a crcok interrupt. if crc is wrong (corrupted packet, with crc on but crcautoclearon is off), the payloadready interr upt will drive the sequenc er to rxtimeout state. 100: to sequenceroff state on a rssi interrupt 101: to sequenceroff state on a syncaddress interrupt 110: to sequenceroff state on a preambledetect interrupt irrespective of this setting, transition to lowpowerselection on a t2 interrupt fromrxtimeout controls the state-machine transition from the receive state on a rxtimeout interrupt (and on payloadready if fromreceive = 011): 00: to receive state via receiverestart 01: to transmit state 10: to lowpowerselection 11: to sequenceroff state note: rxtimeout interrupt is a timeoutrxrssi , timeoutrxpreamble or timeoutsignalsync interrupt.
www.semtech.com page 58 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.9.3. timers two timers (timer1 and timer2) are also available in order to define periodic sequences. these timers are used to ge nerate interrupts, which can trigger transitions of the sequencer. t1 inter rupt is generated (timer1resolution * timer1coefficient) after t2 interrupt or sequencerstart . command. t2 inter rupt is generated (timer2resolution * timer2coefficient) after t1 interrupt . the timer mechanism is summarized on the following diagram. t2 interrupt t1 interrupt timer1 timer2 sequencer start figure 24. timer1 and timer2 mechanism note the timer sequence is completed independently of the actual sequencer state. thus, both timers need to be on to achieve periodic cycling. frompacketreceived controls the state-machine transition from the packetreceived state: 000: to sequenceroff state 001: to transmit on a fifoempty interrupt 010: to lowpowerselection 011: to receive via fs mode, if frequency was changed 100: to receive state (no frequency change)
www.semtech.com page 59 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation table 26 variable description sequencer timer settings timer1resolution resolution of timer1 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms timer2resolution resolution of timer2 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms timer1coefficient multiplying coefficient for timer1 timer2coefficient multiplying coefficient for timer2
www.semtech.com page 60 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.9.4. sequencer state machine the following graphs summarize every possible transition be tween each sequencer state. the sequencer states are highlighted in grey. the transitions are represented by arrows. the condition activating them is described over the transition arrow. for better readability, the start transitions are separated fr om the rest of the graph. transitory states are highlighted in light grey, and exit stat es are represented in red. it is also possible to force the sequencer off by setting the stop bit in regseqconfig1 to 1 at any time. sequencer: ? start ? transitions sequencer: ? state ? machine transmit lowpower selection idle receive packet received rxtimeout if lowpowerselection = 1 on t1 if fromidle = 0 on packetsent if fromtransmit = 1 on payloadready if fromreceive = 001 on crcok if fromreceive = 011 on payloadready if fromreceive = 010 if fromrxtimeout = 01 if fromrxtimeout = 10 if frompacketreceived = 010 if frompacketreceived = 100 via fs mode if frompacketreceived = 011 on packetsent if fromtransmit = 0 via receiverestart if fromrxtimeout = 00 on rxtimeout on t2 on t1 if fromidle = 1 if lowpowerselection = 0 ( mode ?? initial mode ) on rssi if fromreceive = 100 on syncadress if fromreceive = 101 on preamble if fromreceive = 110 if fromrxtimeout = 11 if frompacketreceived = 000 sequencer off standby if idlemode = 0 sleep if idlemode = 1 transmit lowpower selection receive start if fromstart = 00 if fromstart = 01 if fromstart = 10 sequencer off sequencer off & initial mode = sleep or standby on sequencerstart bit rising edge on fifothreshold if fromstart = 11 on payloadready if fromreceive = 011 (crc failed and crcautoclearon =0) figure 25. sequencer state machine
www.semtech.com page 62 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.10. data processing in fsk/ook mode 4.2.10.1. block diagram figure below illustrates th e sx1272/73 dat a processi ng circuit. its role is to interf ace the data to/from the modulator/ demodulator and the uc access points (spi and dio pins ). it also controls all the configuration registers. the circuit contains several control blocks which ar e described in the following paragraphs. control spi packet handler sync recog . dio1 miso mosi sck nss rx tx tx/rx data fifo (+sr ) potential datapaths (data operation mode dependant) dio2 dio0 dio3 dio4 dio5 figure 26. sx1272/73 data processing conceptual view the sx1272/73 implements several data operation modes ea ch with their own data path through the data processing section. depending on the data operation mode selected some control blocks are active whilst others remain disabled. 4.2.10.2. data operation modes the sx1272/73 has two different data op er ation modes selectable by the user: ? continuous mode: each bit transmitted or received is accessed in re al time at the dio2/data pin. this mode may be used if adequate external signal processing is available. ? packet mode (recommended): user only provides/retrieves payload bytes to/from the fifo. the packet is automatically built with preamble, sync word, and optional crc and dc-f ree encoding schemes the reverse operation is performed in reception. the uc processing overhead is hence signific antly reduced compared to continuous mode. depending on the optional features activated (crc, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited. each of these data operation modes is fully described in the following sections.
www.semtech.com page 63 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.11. fifo overview and shift register (sr) in packet mode of operation both data to be transmitted and that has been received are stored in a configurable fifo (first in first out). it is accessed via the spi interface and provides several interrupts for transfer management. the fifo is 1 byte wide hence it only performs byte (paralle l) operations, whereas the demodulator functions serially. a shift register is therefore employed to interface the two device s. in transmit mode it takes bytes from the fifo and outputs them serially (msb first) at the programmed bit rate to the modu lator. similarly, in rx the sh ift register gets bit by bit data from the demodulator and writes th em byte by byte to the fifo. th is is illustrated in figure below. data tx/rx 8 1 sr (8bits) byte0 byte1 fifo msb lsb figure 27. fifo and shift register (sr) note when switching to sleep mode, the fifo can only be used once the modeready flag is set (immediately from all modes except from tx) the fifo size is fixed to 64 bytes. interrupt sources and flags ? fifoempty : fifoempty interrupt source is high when byte 0, i.e. whole fi fo, is empty. otherwise it is low. note that when retrieving data from the fifo, fifoempty is updated on nss fa lling edge, i.e. when fifoempty is updated to low state the currently started read operation mu st be completed. in other words, fifoempty state must be checked after each read operation for a decision on the next one ( fifoempty = 0: more byte(s) to read; fifoempty = 1: no more byte to read). ? fifofull : fifofull interrupt source is high when the last fifo byte , i.e. the whole fifo, is full. otherwise it is low. ? fifooverrunflag : fifooverrunflag is set when a new byte is written by the user (in tx or standby modes) or the sr (in rx mode) while the fifo is already full. da ta is lost and the flag should be cleared by writing a 1, note that the fifo will also be cleared. ? packetsent : packetsent interrupt source goes high when the sr's last bit has been sent. ? fifolevel : threshold can be programmed by fifothreshold in regfifothresh . its behavior is illust rated in figure below.
# of bytes in fifo fifolevel 0 1 b b+1 www.semtech.com page 64 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 28. fifolevel irq source behavior notes - fifolevel interrupt is updated only after a read or write operation on the fifo. thus the interrupt cannot be dynamically updated by only changing the fifothreshold parameter - fifolevel interrupt is valid as long as fifofull does not occur. an empty fifo will restor e its normal operation fifo clearing table below summarizes the status of the fi fo when switching between different modes table 27 from to fifo status comments status of fifo when switching between different modes of the chip 4.2.11.1. sync word recognition overview sync word recognition (als o called pattern recognition) is activated by setting syncon in regsyncconfig . the bit synchronizer must also be activated in conti nuous mode (automatically done in packet mode). the block behaves like a shift register as it continuously co mp ares the incoming data with its internally programmed sync word and sets syncaddressmatch when a match is detected. this is illustrated in figure 29 below. stdby sleep not cleared sleep stdby not cleared stdby/sleep tx not cleared to allow the user to write the fifo in stdby/sleep before tx stdby/sleep rx cleared rx tx cleared rx stdby/sleep not cleared to allow the user to read fifo in stdby/sleep mode after rx tx any cleared
rx data (nrz) dclk bit n-x = sync_value[x] bit n-1 = sync_value[1] bit n = sy nc_value[0] syncaddressmatch www.semtech.com page 65 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 29. sync word recognition during the comparison of the demodulated data, the fi rst bit received is compared with bit 7 (msb) of regsyncvalue1 and the last bit received is compared with bit 0 (lsb) of the last byte whose address is determi ned by the length of the sync word. when the programmed sync word is detected the user can assume th at this incoming packet is for the node and can be processed accordingly. syncaddressmatch is cleared when leaving rx or fifo is emptied. configuration ? size: sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via syncsize in regsyncconfig . in packet mode this field is also used for sync word generation in tx mode. ? value: the sync word va lue is configured in syncvalue(63:0) . in packet mode this field is also used for sync word generation in tx mode. note syncvalue choices containing 0x00 bytes are not allowed packet handler the packet handler is the block used in packet mode. it s functionality is fully described in section 4.2.14. control the control block configures and controls the full chip's beha vio r according to the settings programmed in the configuration registers.
www.semtech.com page 66 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.12. digital io pins mapping six general purpose io pins are availa ble on the sx1272/73 and their configurat ion in continuous or packet mode is controlled through regdiomapping1 and regdiomapping2. table 28 dio mapping, continuous mode diox mapping sleep standby fsrx/tx rx tx 00 syncaddress txready 01 rssi / preambledetect - 10 rxready txready 11 00 01 rssi / preambledetect - 10 11 00 01 10 11 00 timeout - 01 rssi / preambledetect - 10 11 - 00 01 10 timeout - 11 - 00 clkout if rc 01 10 rssi / preambledetect - 11 - plllock modeready modeready dio0 dio1 dio3 dio2 - - - dio5 dio4 - - - - - - - - - - - - modeready modeready dclk data data data clkout clkout tempchange / lowbat tempchange / lowbat tempchange / lowbat plllock data - - - - - table 29 dio mapping, packet mode diox mapping sleep standby fsrx/tx rx tx 00 payloadready packetsent 01 crcok - 10 11 - 00 fifolevel 01 fifoempty 10 fifofull 11 00 fifofull 01 rxready - 10 timeout fifofull 11 syncaddress fifofull 00 fifoempty 01 txready 10 fifoempty 11 fifoempt y 00 - 01 10 timeout - 11 rssi / preambledetect - 00 clkout if rc 01 10 11 - fifoempty modeready fifoempty fifoempty fifoempty dio5 - plllock -data clkout clkout modeready dio4 - plllock - - tempchange / lowbat tempchange / lowbat dio3 - fifoempty dio2 - fifofull fifofull fifofull fifofull fifoempty dio1 - fifolevel fifoempty fifoempty fifolevel fifofull fifofull dio0 - - - tempchange / lowbat tempchange / lowbat
www.semtech.com page 67 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.13. continuous mode 4.2.13.1. general description as illustrated in figure 30 in continuous mode the nrz data to (from) the (d e)modulator is directly accessed by the uc on the bidirectional dio2/data pin. the fifo and packet handler are thus inactive. control spi sync reco g. dio1/dclk miso mosi sck nss rx tx/rx data dio2/data dio0 dio3 dio4 dio5 figure 30. continuous mode conceptual view 4.2.13.2. tx processing in tx mode a synchronous data clock for an external uc is provided on dio1/dclk pin. clock timing with respect to the dat a is illustrated in figure 31 . data is internally sampled on the rising e dge of dclk so the uc can change logic state anytime outside the grayed out setup/hold zone. dclk t_data t_data data (nrz) figure 31. tx processing in continuous mode note the use of dclk is required when the modula tion shaping is enabled (see section 4.2.13.2).
www.semtech.com page 68 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.13.3. rx processing if the bit synchronizer is disabled the raw demodulator output is m ade directly available on data pin and no dclk signal is provided. conversely, if the bit synchronizer is enabled, synchronous clea ned data and clock are made available respectively on dio2/data and dio1/dclk pins. data is sampled on the rising edge of dcl k and updated on t he falling edge as illustrated below. data (nrz) dclk figure 32. rx processing in continuous mode note in continuous mode it is always recommended to enable the bit synchronizer to clean the data signal even if the dclk signal is not used by the uc (bit synchron izer is automatically enabled in packet mode). 4.2.14. packet mode 4.2.14.1. general description in packet mode the nrz data to (from) the (de)modulator is no t d irectly accessed by the uc but stored in the fifo and accessed via the spi interface. in addition the sx1272/73 packet handler performs severa l p acket oriented tasks such as preamble and sync word generation, crc calculation/che ck, whitening/dewhitening of data, manchester encoding/decoding, addr ess filtering, etc. this simplifies software and reduces uc overhead by perform ing these repetitive tasks wi thin the rf chip itself. another important feat ure is ability to fill and empty th e fifo in sleep/stdb y mode to ensure mini mum power consumption when accessing payload data.
control spi packet ha ndler sync re cog. dio1 miso mosi sck nss rx tx data fifo (+ sr) dio2 dio0 dio3 dio4 dio5 www.semtech.com page 69 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 33. packet mode conceptual view note the bit synchronizer is automa tically enabled in packet mode. 4.2.14.2. packet format fixed length packet format fixed length packet format is selected when bit packetformat is set to 0 and payloadlength is set to any value greater than 0. in applications where the packet length is fixed in ad vance, this mode of operatio n may be of interest to minimize rf overhead (no length byte field is required). all nodes, whether tx only, rx only or tx/rx should be programmed with the same packet length value. the length of the payload is limited to 2047 bytes. the length programmed in pa yloadlength relates only to the pa yload which includes the message and the optional address byte. in this mode the payload must contai n at least one byte i.e. address or message byte. an illustration of a fixed length packet is s hown below. it contains the following fields: ? preamble (1010...) ? sync word (network id) ? optional address byte (node id) ? message data ? optional 2-bytes crc checksum
message up to 2047 bytes address byte crc 2-bytes sync word 0 to 8 bytes payload ( min 1 b y te ) crc checksum calculation fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding preamble 0 to 65536 bytes www.semtech.com page 70 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 34. fixed length packet format variable length packet format variable length packet format is selected when bit pa cketformat is set to 1. this mode is useful in applications where the length of the pack e t is not known in advance and can vary over time. it is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. in this mode the length of the payload, indicated by the length byte, is given by the first byte of the fifo and is limited to 255 bytes. note that the length byte itself is not included in its calculation. in th is mode the payload must contain at least 2 bytes i.e. length + address or message byte. an illustration of a variable length packet is shown below. it contains the following fields: ? preamble (1010...) ? sync word (network id) ? length byte ? optional address byte (node id) ? message data
www.semtech.com page 71 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation ? optional 2-bytes crc checksum figure 35. variable length packet format unlimited length packet format unlimited length packet forma t is selected when bit packetformat is set to 0 and payloadlength is set to 0. the user can then transmit and receive packet of arbitrary length and payloadlength register is not used in tx/rx modes for counting the length of the bytes transmitted/received. in tx the data is transmitted depending on the txstartcondition bit. on the rx side the data processing features like address filtering, manchester encoding and data whitening are not available if the sync pattern length is set to zero ( syncon = 0 ). the filling of the fifo in this case can be controlled by the bit fifofillcondition . the crc detection in rx is also not supported in this mode of the packet handler, howeve r crc generation in tx is ope rational. the interrupts like crcok & payloadready are not available either. an unlimited length packet shown belo w is made up of the following fields: ? preamble (1010...). ? sync word (network id). ? optional address byte (node id). ? message data ? optional 2-bytes crc checksum (tx only) figure 36. unlimited length packet format message up to 255 bytes address byte length byte crc 2-bytes sync word 0 to 8 bytes preamble 0 to 65536 bytes payload (min 2 bytes) crc checksum calculation fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding message unlimited length address byte sync word 0 to 8 bytes preamble 0 to 65535 bytes payload fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload dc free data encoding
www.semtech.com page 72 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.14.3. tx processing in tx mode the packet handler dynamically builds the pa cket by performing the following operations on the payload available in the fifo: ? add a programmable number of preamble bytes. ? add a programmable sync word. ? optionally calculating crc over complete payload field (optional length byte + optional address byte + message) and appending the 2 bytes checksum. ? optional dc-free encoding of the data (manchester or whitening). only the payload (including optional address and length fi elds) is required to be provided by the user in the fifo. the transmission of packet data is initiated by the packet handler only if the chip is in tx mode and the transmission condition defined by txstartcondition is fulfilled. if transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condit ion is met. this happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is me t to transmit the packet data. the transmission condition itself is defined as: ? if txstartcondition = 1, the packet handler waits until the first byte is written into the fifo, t hen it starts sending the preamble followed by the sync word and user payload ? if txstartcondition = 0, the packet handler waits until the number of bytes written in the fifo is equal to the number defined in regfifothresh + 1 ? if the condition for transmission was alre ady fulfilled i.e. the fifo was filled in sleep/stdby th en the transmission of packet starts immediately on enabling tx 4.2.14.4. rx processing in rx mode the packet handler extracts the user payl oad to the fifo by performing the following operations: ? receiving the preamble and stripping it off. ? detecting the sync word and stripping it off. ? optional dc-free decoding of data. ? optionally checking the address byte. ? optionally checking crc and reflecting the result on crcok. . only the payload (including optional address and length fields) is made available in the fifo. when the rx mode is enabled the demodulator receives the pr eamble followed by the detecti on of sync word. if fixed length packet format is enabled then the number of bytes received as the payload is given by the payloadlength parameter. in variable length mode the first byte receiv ed after the sync word is interpreted as the length of the received packet. the internal length counter is initializ ed to this received length. the payloadlength register is set to a value which is greater than the maximum expected length of the received packet. if th e received length is greater than the maximum length stored in payloadlength register the packet is discarded other wise the complete packet is received. if the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. if the address matches to the one in the nodeaddress field reception of the data continues otherwise it's stopped. the cr c check is performed if crcon = 1 and the result is available in crcok indicating that the
www.semtech.com page 73 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation crc was successful. an interrupt ( payloadready ) is also generated on dio0 as soon as the payload is available in the fifo. the payload available in the fifo can also be read in sleep/standby mode. if the crc fails the payloadready interrupt is not generated and the fifo is cleared. this function can be overridden by setting crcautoclearoff = 1, forcing the availability of payloadready interrupt and the payload in the fifo even if the crc fails. 4.2.14.5. handling large packets when payloadlength exceeds fifo size (64 byte s) whether in fixed, variable or unlimited length packet format, in addition to packetsent in tx and payloadready or crcok in rx, the fifo interrupts/flags can be used as described below: ? for tx: fifo can be prefilled in slee p/standby but must be refille d ?on-the-fly? duri ng tx with the rest of the payload. 1) pre-fill fifo (in sleep/standby fi rst or directly in tx mode) until fifothreshold or fifofull is set 2) in tx, wait for fifothreshold or fifoempty to be set (i.e. fifo is nearly empty) 3) write bytes into the fifo until fifothreshold or fifofull is set. 4) continue to step 2 until the entire message has been written to the fifo ( packetsent will fire when the last bit of the packet has been sent). ? for rx: fifo must be emptied ?on-the-fly? during rx to prevent fifo overrun. 1) start reading bytes from the fifo when fifoempty is cleared or fifothreshold becomes set. 2) suspend reading from the fifo if fifoempty fires before all bytes of the message have been read 3) continue to step 1 until payloadready or crcok fires 4) read all remaining bytes from the fifo either in rx or sleep/standby mode 4.2.14.6. packet filtering the sx1272/73 packet handler offers several mechanisms for packe t filtering, ensuring that only useful packets are made available to the uc, significantly reducing system power consumption and software complexity. sync word based sync word filtering/recognition is used for identifying the start of the pa yload and also for network identification. as previously described, the sync word recognit ion block is configured (size, value) in regsyncconfig and regsyncvalue(i) registers. this information is used both for appendi ng sync word in tx and filtering packets in rx. every received packet which does not st art with this locally config ured sync word is automat ically discarded and no interrupt is generated. when the sync word is detected paylo ad reception automatically starts and syncaddressmatch is asserted. note sync word values containing 0x00 are forbidden.
www.semtech.com page 74 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation address based address filtering can be enabled via the addressfiltering bits. it adds another level of f iltering above sync word (i.e. sync must match first) and is typically useful in a multi-node networks where a network id is shared between all nodes (sync word) and each node has its own id (address). two address based filtering options are available: ? addressfiltering = 01 : received address field is compared with internal register nodeaddress . if they match then the packet is accepted and processed, otherwise it is discarded. ? addressfiltering = 10 : received address field is compared with internal registers nodeaddress and broadcastaddress . if either is a match, the received packet is accepted and proc essed, otherwise it is discar ded. this additional check with a constant is useful for implementing broadcast in a multi-node networks please note that the received address byte, as part of the pa yloa d, is not stripped off the packet and is made available in the fifo. in addition, nodeaddress and addressfiltering only apply to rx. on tx side, if address filtering is expected, the address byte should simply be put into the fifo like any other byte of the payload. as address filtering requires a sync word match he n ce both features share the same interrupt flag syncaddressmatch . length based in variable length packet mode, payloa dlength must be programmed with the maxi mum payload length permitted. if received length byte is smaller than this maximum then th e packet is accepted and processed, otherwise it is discarded. please note that the received le ngth byte, as p art of the payload, is not stri pped off the packet and is made available in the fifo. to disable this function the user should set the value of the payloa dlength to 2047. crc based the crc check is enabled by setting bit crc on in regpacketconfig1 . it is used for checking the integrity of the message. ? on tx side a two byte crc checksum is calculated on th e payload part of the packet and appended to the end of the message ? on rx side the checksum is calculated on the received pa yload and compared with the two checksum bytes received. the result of the comparison is stored in bit crcok. by default, if the crc check fails then the fifo is automatically cleared and no inte rrupt is generated. this filtering functio n can be disabled via crcautoclearoff bit and in this case, even if crc fa ils, the fifo is not cleared and only payloadready interrupt goes high. please note that in both cases, the two crc checksum bytes ar e stripped off by the packet handler and only the payload is made available in the fifo. two crc implem entations are selected with bit crcwhiteningtype . table 30 crc type crcwhiteningtype polynomial seed value complemented crc description a c code implementation of each crc type is proposed in application section 7 . ccitt 0 (default) x 16 + x 12 + x 5 + 1 0x1d0f yes ibm 1 x 16 + x 15 + x 2 + 1 0xffff no
www.semtech.com page 75 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.2.14.7. dc-free data mechanisms the payload to be transmitted may contain long sequences of 1 's and 0's, which introduces a dc bias in the transmitted signal. the radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. it also introduces data dependencies in the normal operation of the demodu lator. thus it is useful if the transmitted data is random and dc free. for such purposes, two techniques are made available in th e p acket handler: manchester encoding and data whitening. note only one of the two methods can be enabled at a time. manchester encoding manchester encoding/decoding is enabled if dcf ree = 01 and can only be used in packet mode. the nrz data is converted to manchester code by co ding '1' as ?10? and '0' as ?01?. in this case, the maximum chip rate is th e maximu m bit rate given in the specificatio ns section and the actual bit rate is half the chip rate. manchester encoding and decoding is only applied to the payload and crc checksum while preamble and sync word are kept nrz. however , the chip rate from preamble to crc is the same and defined by bitrate in regbitrate (chip rate = bit rate nrz = 2 x bit rate manchester). manchester encoding/decoding is thus transparent with nrz transferred between fifo and mcu. ...sync payload... rf chips @ br ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester off ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester on ... 1 1 1 0 1 0 0 1 0 0 1 1 ... t 1/br 1/br figure 37. manchester encoding/decoding data whitening another technique called whitening or scrambling is widely us ed for randomizing the user data before radio transmission. the data is whitened using a random sequence on the tx side and de-whitened on the rx side using the same sequence. compared to manchester coding, whitening has the added advantage that the nrz data rate is retained i.e. the effective actual bit rate is not halved. the whitening/de-whitening process is enabled if dcf ree = 10 . a 9-bit lfsr is used to generate a random sequence. the payload and 2-byte crc checksum is then xored with this random sequence as shown belo w. the data is de-whitened on the receiver side by xoring with the same random sequence. payload whitening/de-whitening is thus made transparent to the user who still provides/retrieves nrz data to/from the fifo.
x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x 8 lfsr polynomial =x 9 + x 5 + 1 transmit data whitened data www.semtech.com page 76 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 38. data whitening polynomial 4.2.14.8. beacon tx mode in some short range wireless network topologies a repetitive m essage, also known as beacon, is transmitted periodically by a transmitter. the beacon tx mode a llows for the re-transmission of the same packet withou t having to fill the fifo multiple times with the same data. when be aconon in regpacketconfig2 is set to 1 the fifo can be filled only onc e in sleep or stdby mode with the required payload. after a first transmission, fifoempty will go high as usual, bu t the fifo content will be re stored when the chip exits transmit mode. fifoempty , fifofull and fifolevel flags are also restored. this feature is only available in fixed p acket format with the pa yload length smaller than the fifo size. the control of the chip modes (tx-sleep-tx....) can either be undertaken by the microcontroller, or be automated in the top sequencer. see example in section 4.2.14.8 . the beacon tx mode is exited by setting be aconon to 0 and clearing the fifo by setting fifooverrun to 1. 4.2.15. io-homecontrol ? compatibility mode the sx1272/73 features a io-homecontrol ? compatibility mode. please contact your local semtech representative for details on its implementation.
www.semtech.com page 77 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 4.3. spi interface the spi interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to cpol = 0 and cpha = 0 in motorola/freescale nomenclature. only the slave side is implemented. three access modes to the registers are provided: ? single access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. the nss pin goes low at the beginning of the frame and goes high after the data byte. ? burst access: the address byte is followed by several data bytes. the address is automati cally incremented internally between each data byte. this mode is available for both read and write accesses. the nss pin goes low at the beginning of the frame and stay low between each byte . it goes high only afte r the last byte transfer. ? fifo access: if the address byte corr esponds to the address of the fifo, then succeeding data byte will address the fifo. the address is not automatically incremented but is me morized and does not need to be sent between each data byte. the nss pin goes low at the beginning of the frame and stay low between each byte. it goes high only after the last byte transfer. the figure below shows a typical spi single access to a register. figure 39. spi timing diagram (single access) mosi is generated by th e master on the falling edge of sck and is sample d by the slave (i.e. this spi interface) on the rising edge of sck. miso is generated by the slav e on the falling edge of sck. a transfer is always started by the nss pin goin g low. miso is high impedance when nss is high. the first byte is the address byte. it is comprises: ? a wnr bit, which is 1 for write access and 0 for read access. ? then 7 bits of address, msb first. the second byte is a data byte, either s ent on mosi by the master in case of a write access or received by the master on miso in case of read access. the data byte is transmitted msb first. proceeding bytes may be sent on mosi (for write access) or received on miso (for read access) without a rising nss edge and re-sending the address. in fifo mode , if the address was the fifo address then the by tes will be written / read at the fifo address. in burst mode, if the address was not t he fifo address, then it is automatically incremented for each new byte received.
www.semtech.com page 78 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the frame ends when nss goes high. the next frame must st art with an address byte. the single access mode is therefore a special case of fifo / burst mode with only 1 data byte transferred. during the write access the byte transferred from the slave to the master on the miso line is the value of the written register before the write operation.
www.semtech.com page 79 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 5. sx1272/73 analog & rf frontend electronics 5.1. power supply strategy the sx1272/73 employs an internal voltage regulation scheme which provides stable operating voltage, and hence device characteristics, over the full industrial temperature and operating voltage range. this includes up to +17 dbm of rf output power w hich is maintained from 1.8 v to 3.7 v and +20 dbm from 2.4 v to 3.7 v. the sx1272/73 can be powered from any low-noise voltage so urce via pins vbat1 and vb at2. decoupling capacitors should be connected, as suggested in the reference design of the applications section of this document, on vr_pa, vr_dig and vr_ana pins to ensure correct operation of the built-in voltage regulators. 5.2. low battery detector a low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage dropping below a programmable threshold that is adjustable through the register reglowbat . the interrupt signal can be mapped to any of the dio pins by programming regdiomapping . 5.3. frequency synthesis 5.3.1. crystal oscillator the crystal oscillator is the main timing reference of the sx1272/73. it is used as the reference for the pll?s frequency synthesis and as the clock signal for all digital processing. the crystal oscillator startup time, ts_osc , depends on the electrical characterist ics of the crystal reference used, for more information on the electrical s pecification of the crystal see section 7.1 . the crystal connects to the pierce oscillator of pins xta and xtb. the sx1272/73 optimizes the startup time and automatically triggers the pll when the oscillator signal is stable. optionally, an external clock can be used to replace the cry stal oscillator. this typi cally takes the form of a tight tolerance temperature compensated crystal oscillator (tcxo). when using an ex ternal clock so urce the bit tcxoinputon of register regtcxo should be set to 1 and the external clock has to be provided on xta (pin 4). xtb (pin 5) should be left open. the peak-peak amplitude of the input signal must never e xce ed 1.8 v. please consult your tcxo supplier for an appropriate value of decoupling capacitor, c d . xta xtb 32 mhz tcxo nc op vcc gnd c d vcc figure 40. tcxo connection
www.semtech.com page 80 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 5.3.2. clkout output the reference frequency, or a fraction of it, can be provided on dio5 (pin 12) by modifying bits clkout in regdiomapping2 . two typical applications of the clkout output include: ? to provide a clock output for a companion processor, thus saving the cost of an additional oscillator. clkout can be made available in any operation mode except sleep mode and is automatically enabled at power on reset. ? to provide an oscillator refer ence output. measurement of th e clkout signal enables simp le software tr imming of the initial crystal tolerance. note to minimize the current consumption of the sx1272/73, pl ease ensure that the clkout signal is disabled when not required. 5.3.3. pll the local oscillator of the sx1272/73 is der ived from a fractional-n pll that is refe renced to the crystal oscillator circuit. two plls are available for transmit mode operation - either lo w phase noise or low current co nsumption to maximize either transmit power consumption or transmit spectral purity respec tively. both plls feature a programmable bandwidth setting where one of four discrete preset bandwidths may be acce ssed. for reference the relative performance of both low consumption and low phase noise plls, for each programmable bandwidth setting, is shown in the following figure.
www.semtech.com page 81 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 41. typical phase noise performances of the low consumption and low phase noise plls. note in receive mode only the low consumption pll is available. the sx1272/73 pll uses a 19-bit sigma-delta modulator whos e frequency resolution, constant over the whole frequency range, is given by: f step f xosc 2 19 ---------------- =
f rf f step frf 23 0 (,) ? = www.semtech.com page 82 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation the carrier frequency is programmed through regfrf , split across addresses 0x06 to 0x08: note the frf setting is split across 3 byte s . a change in the center frequency w ill only be taken into account when the least significant byte frflsb in regfrf lsb is written. this allo ws the potential for user generation of m-ary fsk at very low bit rates. this is possible where frequency modulation is achieved by direct programming of the programmed rf centre frequency. to enable this func tionality set the fasthopon bit of register regpllhop. 5.3.4. rc oscillator all timing operations in the low-power sleep state of the top level sequencer rely on the accuracy of the internal low- power rc oscillator. this oscillator is automatically calibra ted at the device power-up not requir ing any user input.
www.semtech.com page 83 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 5.4. transmitter description the transmitter of sx1272/73 comprises th e frequency synthesizer, modulator (both lora tm and fsk/ook) and power amplifier blocks, together with the dc biasing and ramping functionality that is provided through the vr_pa block. 5.4.1. architecture description the architecture of the rf front end is shown in the following diagram. here we see that the unregulated pa0 is connected to the rfo pin features a single low power amplifier device. the pa_boost pin is connected to the internally regulated pa1 and pa2 circuits. here pa2 is a high power amplifier that permits continuous operation up to +17 dbm and duty cycled operation up to +20 dbm. for full details of operation at +20 dbm please consult section 5.4.3 . lna rec eiv er chain rfi local os c illator pa 0 pa 1 pa 2 pa _ b o os t rfo figure 42. rf front-end architecture shows the internal pa configuration. 5.4.2. rf power amplifiers three power amplifier blocks, pa0 - pa2, are available in th e sx1272/73. pa0 is a high efficiency amplifier capable of yielding rf power programmable in 1 db steps from -1 dbm to +14 dbm directly into a 50 ohm load with low current consumption. pa0 is connected to pin rfo (pin 24). pa1 and pa2 are both connected to pin pa_boost (pin 27). t here are two potential configurations of these power amplifiers, fixed or programmable. in the fixed configur ation they can deliver up to +20 dbm. in programmable configuration they can provide from +17 dbm to +2 dbm in 1 db programmable steps. naturally, low impedance matching and harmonic filtering is required to ensure rf power delivery and regulatory compliance. (see the applications section of this document for more details). table 31 power amplifier mode selection truth table paselect mode power range pout formula pa0 output on pin rfo -1 to +14 dbm -1 dbm + outputpower pa1 and pa2 combined on pin pa_ - boost +2 to +17 dbm +2 dbm + outputpower power +20 dbm settings (see 5.4.3 ) +5 to +20 dbm +5 dbm + outputpower 0 1 1 pa1+pa2 on pa_boost with high output
www.semtech.com page 84 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation notes - for +20 dbm restrictions on operat ion please consult the following section. - to ensure correct operation at the highest power levels ensure that the current limiter ocptrim is adjusted to permit delivery of the requisite supply current. - if the pa_boost pin is not used it may be left floating. 5.4.3. high power +20 dbm operation the sx1272/73 has a high power +20 dbm capabilit y on pa_boost pin, with the following settings: table 32 register address value for high power default value pa0 or +17dbm description high power pa control high power settings notes - high power settings must be turned off when using pa0 - the over current protection limit should be adapted to the actual power level, in regocp specific absolute maximum ratings and o per ating range restrictions apply to the +20 dbm operation. they are listed in ta b l e 33 and ta b l e 34 . table 33 operating range, +20 dbm operation symbol description min max unit dc_20dbm duty cycle of transmission at +20 dbm output - 1 % vswr_20dbm maximum vswr at antenna port, +20 dbm output - 3:1 - table 34 operating range, +20 dbm operation symbol description min max unit vddop_20dbm supply voltage, +20 dbm output 2.4 3.7 v the duty cycle of transmission at +20 dbm is limited to 1%, with a maximum vswr of 3:1 at antenna port, over the standard operating range (-40 to +85 c). for any other operating conditions, contact your semtech representative. regpadac 0x5a 0x87 0x84
www.semtech.com page 85 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 5.4.4. over current protection the power amplifiers of sx1272/73 are protected against curren t over supply in adverse rf load conditions by the over current protection block. this has the added benef it of protecting battery chemistries with limited peak current capability and minimising worst case pa consumption in battery life ca lculations. the current limiter value is controlled by the ocptrim bits in regocp and is calculated accordi ng to the following formulas: table 35 trimming of the ocp current ocptrim i max imax formula 45 to 120 ma 45 + 5* ocptrim [ma] 130 to 240 ma -30 + 10* ocptrim [ma] 240 ma 240 [ma] note imax sets a limit on the current drain of the po wer amplifier only, hence the maximum current drain of the sx1272/ 73 is equal to imax + iddfs . 5.5. receiver description 5.5.1. overview the sx1272/73 features a digital receiver with the analog to digital conversion process performed directly following the lna-mixer block. in addition to the lora tm modulation scheme the low-if receiver is abl e to demodulate ask, ook, (g)fsk and (g)msk modulation. all filtering, demodulation, gain control, synchronization and packet handling is performed digitally allowing a hi gh degree of programmable flexibility. the receiver also has au tomatic gain calibration, this improves the precision of rssi meas urement and enhances image rejection. 5.5.2. receiver enabled and receiver active states in the receiver operating mode two states of functionality are defined. upon initial transition to receiver operating mode the receiver is in the ?receiver-enabled? state. in this state the receiver awaits for either the user defined valid preamble or rs si detection criterion to be fulfilled. once met the receiver enters ?receiver-active? state. in th is second state the received signal is processed by the pack et engine and top level sequencer. for a complete description of the digital functions of the sx1272/73 receiver please see section 5.5 of the datasheet. 0 to 15 16 to 27 27+
www.semtech.com page 86 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 43. receiver block diagram 5.5.3. automatic gain control in fsk/ook mode the agc feature allows receiver to hand le a wide rx input dynamic range from th e sensitivity level up to maximum input level of 0 dbm or more, whilst optimizing the system linearity. the following table shows typical nf and iip3 performances for the sx1272/73 lna gains available. table 36 lna gain control and performances rx input level (pin) gain setting lnagain relative lna gain [db] nf [db] iip3 [dbm] pin <= agcthresh1 g1 ?001? 0 db 7 -12 agcthresh1 < pin <= agcthresh2 g2 ?010? -6 db 11 -8 agcthresh2 < pin <= agcthresh3 g3 ?011? -12 db 16 -5 agcthresh3 < pin <= agcthresh4 g4 ?100? -24 db 26 5 agcthresh4 < pin <= agcthresh5 g5 ?110? -26 db 34 10 agcthresh5 < pin g6 ?111? -48 db 44 10
towards -125 dbm ? a g c r e f e r e n c e ? a g c t h r e s h 1 ? a g c t h r e s h 2 ? a g c t h r e s h 3 ? a g c t h r e s h 4 pin [dbm] ? a g c t h r e s h 5 agcstep1 agcstep2 agcstep3 agcstep4 agcstep5 g1 g2 g3 g4 g5 g6 higher sensitivity lower linearity lower noise figure lower sensitivity higher linearity higher noise figure www.semtech.com page 87 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 44. agc steps definition the agc reference power level is determined as follows: agc reference [dbm]=-174 dbm + 10 * log(2 * rx bw ) + snr + agcreferencelevel with snr = 8 db (considered a fixed value). a detailed description of the receiver setup to e nable the agc is provided in section 4.2.7 . 5.5.4. rssi in fsk/ook mode the rssi provides a measure of the incoming signal power at rf input port measured within the receiver bandwidth. the signal power is available in rssivalue . this value is absolute in units of dbm an d with a resolution of 0.5 db. the formula below relates the register value to the absolut e input signal level at the rf input port: ? ? ? ? db rssioffset dbmlevelrf rssivalue ? ? ? ? 2 the rssi value can be compensated to take into account the loss in the matching network or even the gain of an additional lna by using rssioffset . the offset can be chosen in 1 db steps from -16 to +15 db. when compensation is applied the effective signal strength is read as follows: ?? 2 rssivalue dbmrssi ?? the rssi value is smoothed on a user de fined number of measured rssi samples. the precision of the rssi value is related to the number of rssi samples used. rssismoothing selects the number of rssi samples from a minimum of 2 samples up to 256 samples in increments of power of 2. ta b l e 37 gives the estimation of the rssi accuracy for a 10 db snr and response time versus the number of rssi samples programmed in rs sismoothing .
www.semtech.com page 88 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation table 37 rssismoothing options the rssi is calibrated when the image and rssi ca libration process is launched. please see section ta b l e 4.2.3.8 for details. 5.5.5. rssi and snr in lora tm mode the rssi values reported by the lora tm modem differ from those expressed by the fsk/ook modem. the following formula shows the method us ed to interpret the lora tm rssi values: rssi (dbm) = -139 + rssi , (with lnaboost on) the same formula can be re-used to evaluate the signal strength of the received packet: packet strength (dbm) = -139 + packetrssi * 0.25 , (with lnaboost on and snr >= 0) due to the nature of the lora modulation, it is possible to re ceive packets below the noise floor. in this situation, the snr is used in conjunction of the packetrssi to co mpute the signal strength of the received packet: packet strength (dbm) = -139 + packetrssi + packetsnr * 0.25, (with lnaboost on and snr < 0) note: 1. packetrssi (in regpktrssivalue), is an averaged version of rssi (in regrssivalue). rssi can be read at any time (during packet reception or not), and should be averaged to give more precise results. 2. the constants, -139, may vary with the front-end setup of the sx1272 ( lnaboost on or off, presence of an external lna, mismatch at the lna input?). it is recommended to adju st these values with a single-point calibration procedure to increase rssi accuracy. 3. as signal strength increases (rssi>-100dbm), the linearity of packetrssi is not guaranteed a nd results will diverge from the ideal 1db/db curve. when very good rssi precision is required over the whole dynamic range of the receiver, two options are proposed: - rssi in regrssivalue offers better linearity. rssi can be sampled during the reception of the payload (between validheader and rxdone irq), and used to extract a more high-signal rssi measurement. rssi is updated every 1/bw (i.e. 8us in 125khz mode , 4us in 250khz, etc?) - when snr>=0, the standard formula can be adjusted to correct the slope: rssi = -139+16/15 * packetrssi rssismoothing number of samples estimated accuracy response time ?000? 2 6 db ?001? 4 5 db ?010? 8 4 db ?011? 16 3 db ?100? 32 2 db ?101? 64 1.5 db ?110? 128 1.2 db ?111? 256 1.1 db >@ >@ ms khz rxbw ing rssismooth ? 4 2 1
www.semtech.com page 89 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 5.5.6. channel filter the role of the channel filter is to reject noise and interference outside of the wanted channel. the sx1272/73 channel filtering is implemented with a 16-tap finite impulse response (fir ) filter. rejection of the filter is high enough that the fi lter stop-band performance is not the dominant influence on adjacent channel rejection performance. this is instead limited by the sx1272/73 pll phase noise. note to respect sampling criterion in the decimation chain of th e receiver, the communication bit rate cannot be set at a higher than twice the single side receiver bandwidth (bitrate < 2 x rxbw) the programmed single side bandwidth rxbw of the channel filter is determined by the parameters rxbwmant and rxbwexp in regrxbw: the following channel filter bandwidths are hence acce ssible in the case of a 32 mhz reference oscillator. table 38 available rxbw settings rxbwmant (binary/value) rxbwexp (decimal) rxbw (khz) fsk / ook 5.5.7. temperature measurement a stand alone temperature measurement block is used in orde r to measure the temperature in all mode except sleep and standby. it is enabled by default and can be stopped by setting tempmonitoroff to 1. the result of the measurement is stored in tempvalue in regtemp . 10b / 24 7 2.6 01b / 20 7 3.1 00b / 16 7 3.9 10b / 24 6 5.2 01b / 20 6 6.3 00b / 16 6 7.8 10b / 24 5 10.4 01b / 20 5 12.5 00b / 16 5 15.6 10b / 24 4 20.8 01b / 20 4 25.0 00b / 16 4 31.3 10b / 24 3 41.7 01b / 20 3 50.0 00b / 16 3 62.5 10b / 24 2 83.3 01b / 20 2 100.0 00b / 16 2 125.0 10b / 24 1 166.7 01b / 20 1 200.0 00b / 16 1 250.0 other settings reserved rxbw fxosc rxbwmant 2 rxbwexp 2+ ? ----------------------------------------------------------------- - =
www.semtech.com page 90 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation due to process variations the absolute accuracy of the result is +/- 10 c. higher precision requires a calibration procedure at a known temperature. the figure below shows the influence of just such a calibration process. for more information, including source code, please consult the applications section of this document. figure 45. temperature sensor response
www.semtech.com page 91 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 6. description of the registers the register mapping depends upon whether fsk/ook or lora tm mode has been selected. the following table summarises the location and function of each register and gi ves an overview of the changes in register mapping between both modes of operation. 6.1. register table summary table 39 registers summary address register name reset (por) default (fsk) description fsk/ook mode lora tm mode fsk mode lora tm mode 0x00 regfifo 0x00 fifo read/write access 0x01 regopmode 0x01 operating mode & lora tm / fsk selection 0x02 regbitratemsb unused 0x1a bit rate setting, most significant bits 0x03 regbitratelsb 0x0b bit rate setting, least significant bits 0x04 regfdevmsb 0x00 frequency deviation setting, most significant bits 0x05 regfdevlsb 0x52 frequency deviation setting, least significant bits 0x06 regfrfmsb 0xe4 rf carrier frequency, most significant bits 0x07 regfrfmid 0xc0 rf carrier frequency, intermediate bits 0x08 regfrflsb 0x00 rf carrier frequency, least significant bits 0x09 regpaconfig 0x0f pa selection and output power control 0x0a regparamp 0x19 control of pa ramp time, low phase noise pll 0x0b regocp 0x2b over current protection control 0x0c reglna 0x20 lna settings 0x0d regrxconfig regfifoaddrptr 0x08 0x1e afc, agc, ctrl fifo spi pointer 0x0e regrssiconfig regfifotxba - seaddr 0x02 rssi start tx data 0x0f regrssicollision regfiforxba - seaddr 0x0a rssi collision detector start rx data 0x10 regrssithresh fiforxcurren - taddr 0xff rssi threshold control start ? address ? of ? last ? packet ? received 0x11 regrssivalue regirqflagsmask n/a n/a rssi value in dbm optional irq flag mask 0x12 regrxbw regirqflags 0x15 channel filter bw control irq flags 0x13 regafcbw regrxnbbytes 0x0b afc channel filter bw number of received bytes 0x14 regookpeak regrxheadercnt valuemsb 0x28 ook demodulator number of valid headers received 0x15 regookfix regrxheadercnt valuelsb 0x0c threshold of the ook demod 0x16 regookavg regrxpacketcnt valuemsb 0x12 average of the ook demod number of valid packets received 0x17 reserved17 regrxpacketcnt valuelsb 0x47 - 0x18 reserved18 regmodemstat 0x32 - live lora tm ? modem status 0x19 reserved19 regpktsnrvalue 0x3e - espimation of last packet snr 0x1a regafcfei regpktrssivalue 0x00 n/a afc and fei control rssi of last packet
www.semtech.com page 92 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 0x1b regafcmsb regrssivalue 0x00 n/a frequency correction value of the afc current rssi 0x1c regafclsb reghopchannel 0x00 n/a fhss start channel 0x1d regfeimsb regmodemconfig 1 0x00 n/a value of the calculated frequency error modem phy config 1 0x1e regfeilsb regmodemconfig 2 0x00 n/a modem phy config 2 0x1f regpreamblede - tect regsymbtimeout lsb 0x40 0xaa settings of the preamble detector receiver timeout value 0x20 regrxtimeout1 regpreamblemsb 0x00 timeout rx request and rssi size of preamble 0x21 regrxtimeout2 regpreamblelsb 0x00 timeout rssi and pay - loadready 0x22 regrxtimeout3 regpay - loadlength 0x00 timeout rssi and syncad - dress lora tm ? payload length 0x23 regrxdelay regmaxpayloadl ength 0x00 delay between rx cycles loratm maximum pay - load length 0x24 regosc reghopperiod 0x05 0x07 rc oscillators settings, clk - out frequency fhss hop period 0x25 regpreamblemsb regfiforxbytead dr 0x00 preamble length, msb address of last byte written in fifo 0x26 regpreamblelsb reserved 0x03 preamble length, lsb lora tm rx data pointer 0x27 regsyncconfig 0x93 sync word recognition control reserved 0x28 regsyncvalue1 regfeimsb 0x55 0x01 sync word bytes, 1 through 8 estimated frequency error 0x29 regsyncvalue2 regfeimib 0x55 0x01 0x2a regsyncvalue3 regfeilsb 0x55 0x01 0x2b- 0x2f regsyncvalue4 reserved 0x55 0x01 reserved 0x2c regsyncvalue5 regrssiwide - band 0x55 0x01 wideband rssi meas - urement 0x2d- 2f regsyncvalue6-8 reserved 0x55 0x01 reserved 0x30 regpacketconfig1 0x90 packet mode settings 0x31 regpacketconfig2 regdetectopti - mize 0x40 packet mode settings lora detection optimize for sf6 0x32 regpayloadlength reserved 0x40 payload length setting reserved 0x33 regnodeadrs reginvertiq 0x00 node address invert lora i and q sig - nals 0x34 regbroadcastadrs reserved 0x00 broadcast address reserved 0x35 regfifothresh 0x0f 0x8f fifo threshold, tx start condi - tion 0x36 regseqconfig1 0x00 top level sequencer settings 0x37 regseqconfig2 regdetection - threshold 0x00 top level sequencer settings change the lora detec - tion threshold for sf6 0x38 regtimerresol reserved 0x00 timer 1 and 2 resolution control reserved address register name reset (por) default (fsk) description fsk/ook mode lora tm mode fsk mode lora tm mode
www.semtech.com page 93 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation notes - reset values are automatically re freshed in the chip at power on reset - default values are the semtech recommended regi ster values, optimizing the device operation - registers for which the default value differs from the rese t value are denoted by an * in the tables of section 6.2 0x39 regtimer1coef regsyncword 0xf5 0x12 timer 1 setting lora sync word 0x3a regtimer2coef reserved 0x20 timer 2 setting reserved 0x3b regimagecal 0x82 0x02 image calibration engine con - trol 0x3c regtemp - temperature sensor value 0x3d reglowbat 0x02 low battery indicator settings 0x3e regirqflags1 0x80 n/a status register: pll lock state, timeout, rssi 0x3f regirqflags2 0x40 n/a status register: fifo handling flags, low battery 0x40 regdiomapping1 0x00 mapping of pins dio0 to dio3 0x41 regdiomapping2 0x00 mapping of pins dio4 and dio5, clkout frequency 0x42 regversion 0x22 semtech id relating the silicon revision 0x43 regagcref 0x13 adjustment of the agc thresholds 0x44 regagcthresh1 0x0e 0x45 regagcthresh2 0x5b 0x46 regagcthresh3 0xdb 0x4b regpllhop 0x2e control the fast frequency hopping mode 0x58 regtcxo 0x09 tcxo or xtal input setting 0x5a regpadac 0x84 higher power settings of the pa 0x5c regpll 0xd0 control of the pll bandwidth 0x5e regplllowpn 0xd0 control of the low phase noise pll bandwidth 0x6c regformertemp - stored temperature during the former iq calibration 0x70 regbitratefrac 0x00 fractional part in the bit rate division ratio address register name reset (por) default (fsk) description fsk/ook mode lora tm mode fsk mode lora tm mode
www.semtech.com page 94 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 6.2. fsk/ook mode register map this section details the sx1272/73 register mapping and the precise contents of each register in fsk/ook mode. convention: r: read, w: write, t:trigger, c: clear table 40 register map name (address) bits variable name mode default value fsk/ook description regfifo (0x00) 7-0 fifo rw 0x00 fifo data input/output registers for common settings regopmode (0x01) 7 longrangemode r 0x00 0 ? fsk/ook mode 1 ? lora tm mode this bit can be modified only in sleep mode. a write operation on other device modes is ignored. 6-5 modulationtype rw 0x00 modulation scheme: 00 ? fsk 01 ? ook 10 -11 ? reserved 4-3 modulationshaping rw 0x00 data shaping: in fsk: 00 ? no shaping 01 ? gaussian filter bt = 1.0 10 ? gaussian filter bt = 0.5 11 ? gaussian filter bt = 0.3 in ook: 00 ? no shaping 01 ? filtering with f cutoff = bit_rate 10 ? filtering with f cutoff = 2*bit_rate (for bit_rate < 125 kbps) 11 ? reserved 2-0 mode rw 0x01 transceiver modes 000 ? sleep mode 001 ? stdby mode 010 ? fs mode tx (fstx) 011 ? transmitter mode (tx) 100 ? fs mode rx (fsrx) 101 ? receiver mode (rx) 110 ? reserved 111 ? reserved regbitratemsb (0x02) 7-0 bitrate(15:8) rw 0x1a msb of bit rate (chip rate if manchester encoding is enabled) regbitratelsb (0x03) 7-0 bitrate(7:0) rw 0x0b lsb of bit rate (chip rate if manchester encoding is enabled) default value: 4.8 kbps bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- =
www.semtech.com page 95 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regfdevmsb (0x04) 7-6 unused r 0x00 unused 5-0 fdev(13:8) rw 0x00 msb of the frequency deviation regfdevlsb (0x05) 7-0 fdev(7:0) rw 0x52 lsb of the frequency deviation default value: 5 khz regfrfmsb (0x06) 7-0 frf(23:16) rw 0xe4 msb of the rf carrier frequency regfrfmid (0x07) 7-0 frf(15:8) rw 0xc0 msb of the rf carrier frequency regfrflsb (0x08) 7-0 frf(7:0) rw 0x00 lsb of rf carrier frequency default value: 915.000 mhz the rf frequency is taken into account internally only when: - entering fsrx/fstx modes - re-starting the receiver registers for the transmitter regpaconfig (0x09) 7 paselect rw 0x00 selects pa output pin 0 ? rfo pin. maximum power of +13 dbm 1 ? pa_boost pin. maximum power of +20 dbm 6-4 unused r 0x00 unused 3-0 outputpower rw 0x0f output power setting, with 1db steps pout = 2 + outputpower [dbm], on pa_boost pin pout = -1 + outputpower [dbm], on rfo pin regparamp (0x0a) 7-5 unused r - unused 4 lowpntxplloff rw 0x01 select a higher power, lower phase noise pll only when the transmitter is used: 0 ? standard pll used in rx mode, lower pn pll in tx 1 ? standard pll used in both tx and rx modes 3-0 paramp rw 0x09 rise/fall time of ramp up/down in fsk 0000 ? 3.4 ms 0001 ? 2 ms 0010 ? 1 ms 0011 ? 500 us 0100 ? 250 us 0101 ? 125 us 0110 ? 100 us 0111 ? 62 us 1000 ? 50 us 1001 ? 40 us (d) 1010 ? 31 us 1011 ? 25 us 1100 ? 20 us 1101 ? 15 us 1110 ? 12 us 1111 ? 10 us name (address) bits variable name mode default value fsk/ook description fdev fstep fdev 15 0 (,) u = frf fstep frf 23 0 ; u =
www.semtech.com page 96 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regocp (0x0b) 7-6 unused r 0x00 unused 5 ocpon rw 0x01 enables overload current protection (ocp) for the pa: 0 ? ocp disabled 1 ? ocp enabled 4-0 ocptrim rw 0x0b trimming of ocp current: i max = 45+5*ocptrim [ma] if ocptrim <= 15 (120 ma) / i max = -30+10*ocptrim [ma] if 15 < ocptrim <= 27 (130 to 240 ma) i max = 240ma for higher settings default i max = 100ma registers for the receiver reglna (0x0c) 7-5 lnagain rw 0x01 lna gain setting: 000 ? reserved 001 ? g1 = highest gain 010 ? g2 = highest gain ? 6 db 011 ? g3 = highest gain ? 12 db 100 ? g4 = highest gain ? 24 db 101 ? g5 = highest gain ? 36 db 110 ? g6 = highest gain ? 48 db 111 ? reserved note: reading this address always returns the current lna gain (which may be different from what had been previously selected if agc is enabled. 4-2 - r 0x00 unused 1-0 lnaboost rw 0x00 improves the system noise figure at the expense of rx current consumption: 00 ? default setting, meeting the specification 11 ? improved sensitivity regrxconfig (0x0d) 7 restartrxoncollision rw 0x00 turns on the mechanism restarting the receiver automatically if it gets saturated or a packet collision is detected 0 ? no automatic restart 1 ? automatic restart on 6 restartrxwithoutplllock wt 0x00 triggers a manual restart of the receiver chain when set to 1. use this bit when there is no frequency change, restartrxwithplllock otherwise. 5 restartrxwithplllock wt 0x00 triggers a manual restart of the receiver chain when set to 1. use this bit when there is a frequency change, requiring some time for the pll to re-lock. 4 afcautoon rw 0x00 0 ? no afc performed at receiver startup 1 ? afc is performed at each receiver startup 3 agcautoon rw 0x01 0 ? lna gain forced by the lnagain setting 1 ? lna gain is controlled by the agc 2-0 rxtrigger rw 0x06 * selects the event triggering agc and/or afc at receiver startup. see table table 23 for a description. name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 97 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regrssiconfig (0x0e) 7-3 rssioffset rw 0x00 signed rssi offset, to compensate for the possible losses/gains in the front-end (lna, saw filter...) 1db / lsb, 2?s complement format 2-0 rssismoothing rw 0x02 defines the number of samples taken to average the rssi result: 000 ? 2 samples used 001 ? 4 samples used 010 ? 8 samples used 011 ? 16 samples used 100 ? 32 samples used 101 ? 64 samples used 110 ? 128 samples used 111 ? 256 samples used regrssicollision (0x0f) 7-0 rssicollisionthreshold rw 0x0a sets the threshold used to consider that an interferer is detected, witnessing a packet collision. 1db/lsb (only rssi increase) default: 10db regrssithresh (0x10) 7-0 rssithreshold rw 0xff rssi trigger level for the rssi interrupt: - rssithreshold / 2 [dbm] regrssivalue (0x11) 7-0 rssivalue r - absolute value of the rssi in dbm, 0.5db steps. rssi = - rssivalue/2 [dbm] regrxbw (0x12) 7 unused r - unused 6-5 reserved rw 0x00 reserved 4-3 rxbwmant rw 0x02 channel filter bandwidth control: 00 ? rxbwmant = 16 10 ? rxbwmant = 24 01 ? rxbwmant = 20 11 ? reserved 2-0 rxbwexp rw 0x05 channel filter bandwidth control: fsk mode: rxbw fxosc rxbwmant 2 rxbwexp 2+ ? ----------------------------------------------------------------- - = regafcbw (0x13) 7-5 reserved rw 0x00 reserved 4-3 rxbwmantafc rw 0x01 rxbwmant parameter used during the afc 2-0 rxbwexpafc rw 0x03 rxbwexp parameter used during the afc regookpeak (0x14) 7-6 reserved rw 0x00 reserved 5 bitsyncon rw 0x01 enables the bit synchronizer. 0 ? bit sync disabled (not possible in packet mode) 1 ? bit sync enabled 4-3 ookthreshtype rw 0x01 selects the type of threshold in the ook data slicer: 00 ? fixed threshold 10 ? average mode 01 ? peak mode (default) 11 ? reserved 2-0 ookpeaktheshstep rw 0x00 size of each decrement of the rssi threshold in the ook demodulator: 000 ? 0.5 db 001 ? 1.0 db 010 ? 1.5 db 011 ? 2.0 db 100 ? 3.0 db 101 ? 4.0 db 110 ? 5.0 db 111 ? 6.0 db name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 98 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regookfix (0x15) 7-0 ookfixedthreshold rw 0x0c fixed threshold for the data slicer in ook mode floor threshold for the data slicer in ook when peak mode is used regookavg (0x16) 7-5 ookpeakthreshdec rw 0x00 period of decrement of the rssi threshold in the ook demodulator: 000 ? once per chip 001 ? once every 2 chips 010 ? once every 4 chips 011 ? once every 8 chips 100 ? twice in each chip 101 ? 4 times in each chip 110 ? 8 times in each chip 111 ? 16 times in each chip 4 reserved rw 0x01 reserved 3-2 ookaverageoffset rw 0x00 static offset added to the threshold in average mode in order to reduce glitching activity (ook only): 00 ? 0.0 db 10 ? 4.0 db 01 ? 2.0 db 11 ? 6.0 db 1-0 ookaveragethreshfilt rw 0x02 filter coefficients in average mode of the ook demodulator: 00 ? f c chip rate / 32. 01 ? f c chip rate / 8. 10 ? f c chip rate / 4. 11 ? f c chip rate / 2. regres17 to regres19 7-0 reserved rw 0x47 0x32 0x3e reserved. keep the reset values. regafcfei (0x1a) 7-5 unused r - unused 4 agcstart wt 0x00 triggers an agc sequence when set to 1. 3 reserved rw 0x00 reserved 2 unused - - unused 1 afcclear wc 0x00 clear afc register set in rx mode. always reads 0. 0 afcautoclearon rw 0x00 only valid if afcautoon is set 0 ? afc register is not cleared at the beginning of the automatic afc phase 1 ? afc register is cleared at the beginning of the automatic afc phase regafcmsb (0x1b) 7-0 afcvalue(15:8) rw 0x00 msb of the afcvalue, 2?s complement format. can be used to overwrite the current afc value regafclsb (0x1c) 7-0 afcvalue(7:0) rw 0x00 lsb of the afcvalue, 2?s complement format. can be used to overwrite the current afc value regfeimsb (0x1d) 7-0 feivalue(15:8) rw - msb of the measured frequency offset, 2?s complement. must be read before regfeilsb. regfeilsb (0x1e) 7-0 feivalue(7:0) rw - lsb of the measured frequency offset, 2?s complement frequency error = feivalue x fstep name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 99 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regpreambledetect (0x1f) 7 preambledetectoron rw 0x01 * enables preamble detector when set to 1. the agc settings supersede this bit during the startup / agc phase. 0 ? turned off 1 ? turned on 6-5 preambledetectorsize rw 0x01 * number of preamble bytes to detect to trigger an interrupt 00 ? 1 byte 10 ? 3 bytes 01 ? 2 bytes 11 ? reserved 4-0 preambledetectortol rw 0x0a * number or chip errors tolerated over preambledetectorsize. 4 chips per bit. regrxtimeout1 (0x20) 7-0 timeoutrxrssi rw 0x00 timeout interrupt is generated timeoutrxrssi *16*t bit after switching to rx mode if rssi interrupt doesn?t occur (i.e. rssivalue > rssithreshold) 0x00: timeoutrxrssi is disabled regrxtimeout2 (0x21) 7-0 timeoutrxpreamble rw 0x00 timeout interrupt is generated timeoutrxpreamble *16*t bit after switching to rx mode if preamble interrupt doesn?t occur 0x00: timeoutrxpreamble is disabled regrxtimeout3 (0x22) 7-0 timeoutsignalsync rw 0x00 timeout interrupt is generated timeoutsignalsync *16*t bit after the rx mode is programmed, if syncaddress doesn?t occur 0x00: timeoutsignalsync is disabled regrxdelay (0x23) 7-0 interpacketrxdelay rw 0x00 additional delay before an automatic receiver restart is launched: delay = interpacke trxdelay*4*tbit rc oscillator registers regosc (0x24) 7-4 unused r - unused 3 rccalstart wt 0x00 triggers the calibration of the rc oscillator when set. always reads 0. rc calibration must be triggered in standby mode. 2-0 clkout rw 0x07 * selects clkout frequency: 000 ? fxosc 001 ? fxosc / 2 010 ? fxosc / 4 011 ? fxosc / 8 100 ? fxosc / 16 101 ? fxosc / 32 110 ? rc (automatically enabled) 111 ? off packet handling registers regpreamblemsb (0x25) 7-0 preamblesize(15:8) rw 0x00 size of the preamble to be sent (from txstartcondition fulfilled). (msb byte) regpreamblelsb (0x26) 7-0 preamblesize(7:0) rw 0x03 size of the preamble to be sent (from txstartcondition fulfilled). (lsb byte) name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 100 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regsyncconfig (0x27) 7-6 autorestartrxmode rw 0x02 controls the automatic restart of the receiver after the reception of a valid packet (payloadready or crcok): 00 ? off 01 ? on, without waiting for the pll to re-lock 10 ? on, wait for the pll to lock (frequency changed) 11 ? reserved 5 preamblepolarity rw 0x00 sets the polarity of the preamble 0 ? 0xaa (default) 1 ? 0x55 4 syncon rw 0x01 enables the sync word generation and detection: 0 ? off 1 ? on 3 fifofillcondition rw 0x00 fifo filling condition: 0 ? if syncaddress interrupt occurs 1 ? as long as fifofillcondition is set 2-0 syncsize rw 0x03 size of the sync word: ( syncsize + 1) bytes, ( syncsize ) bytes if iohomeon =1 regsyncvalue1 (0x28) 7-0 syncvalue(63:56) rw 0x01 * 1 st byte of sync word. (msb byte) used if syncon is set. regsyncvalue2 (0x29) 7-0 syncvalue(55:48) rw 0x01 * 2 nd byte of sync word used if syncon is set and (syncsize +1) >= 2. regsyncvalue3 (0x2a) 7-0 syncvalue(47:40) rw 0x01 * 3 rd byte of sync word. used if syncon is set and (syncsize +1) >= 3. regsyncvalue4 (0x2b) 7-0 syncvalue(39:32) rw 0x01 * 4 th byte of sync word. used if syncon is set and (syncsize +1) >= 4. regsyncvalue5 (0x2c) 7-0 syncvalue(31:24) rw 0x01 * 5 th byte of sync word. used if syncon is set and (syncsize +1) >= 5. regsyncvalue6 (0x2d) 7-0 syncvalue(23:16) rw 0x01 * 6 th byte of sync word. used if syncon is set and (syncsize +1) >= 6. regsyncvalue7 (0x2e) 7-0 syncvalue(15:8) rw 0x01 * 7 th byte of sync word. used if syncon is set and (syncsize +1) >= 7. regsyncvalue8 (0x2f) 7-0 syncvalue(7:0) rw 0x01 * 8 th byte of sync word. used if syncon is set and (syncsize +1) = 8. name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 101 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regpacketconfig1 (0x30) 7 packetformat rw 0x01 defines the packet format used: 0 ? fixed length 1 ? variable length 6-5 dcfree rw 0x00 defines dc-free encoding/decoding performed: 00 ? none (off) 01 ? manchester 10 ? whitening 11 ? reserved 4 crcon rw 0x01 enables crc calculation/check (tx/rx): 0 ? off 1 ? on 3 crcautoclearoff rw 0x00 defines the behavior of the packet handler when crc check fails: 0 ? clear fifo and restart new packet reception. no payloadready interrupt issued. 1 ? do not clear fifo. payloadready interrupt issued. 2-1 addressfiltering rw 0x00 defines address based filtering in rx: 00 ? none (off) 01 ? address field must match nodeaddress 10 ? address field must match nodeaddress or broadcastaddress 11 ? reserved 0 crcwhiteningtype rw 0x00 selects the crc and whitening algorithms: 0 ? ccitt crc implementation with standard whitening 1 ? ibm crc implementation with alternate whitening regpacketconfig2 (0x31) 7 unused r - unused 6 datamode rw 0x01 data processing mode: 0 ? continuous mode 1 ? packet mode 5 iohomeon rw 0x00 enables the io-homecontrol ? compatibility mode 0 ? disabled 1 ? enabled 4 iohomepowerframe rw 0x00 reserved - linked to io-homecontrol ? compatibility mode 3 beaconon rw 0x00 enables the beacon mode in fixed packet format 2-0 payloadlength(10:8) rw 0x00 packet length most significant bits regpayloadlength (0x32) 7-0 payloadlength(7:0) rw 0x40 if packetformat = 0 (fixed), payload length. if packetformat = 1 (variable), max length in rx, not used in tx. regnodeadrs (0x33) 7-0 nodeaddress rw 0x00 node address used in address filtering. regbroadcastadrs (0x34) 7-0 broadcastaddress rw 0x00 broadcast address used in address filtering. name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 102 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regfifothresh (0x35) 7 txstartcondition rw 0x01 * defines the condition to start packet transmission: 0 ? fifolevel (i.e. the number of bytes in the fifo exceeds fifothreshold) 1 ? fifoempty goes low (i.e. at least one byte in the fifo) 6 unused r - unused 5-0 fifothreshold rw 0x0f used to trigger fifolevel interrupt, when: number of bytes in fifo >= fifothreshold + 1 sequencer registers regseqconfig1 (0x36) 7 sequencerstart wt 0x00 controls the top level sequencer when set to ?1?, executes the ?start? transition. the sequencer can only be enabled when the chip is in sleep or standby mode. 6 sequencerstop wt 0x00 forces the sequencer off. always reads ?0? 5 idlemode rw 0x00 selects chip mode during the state: 0: standby mode 1: sleep mode 4-3 fromstart rw 0x00 controls the sequencer transition when sequencerstart is set to 1 in sleep or standby mode: 00: to lowpowerselection 01: to receive state 10: to transmit state 11: to transmit state on a fifolevel interrupt 2 lowpowerselection rw 0x00 selects the sequencer lowpower state after a to lowpowerselection transition: 0: sequenceroff state with chip on initial mode 1: idle state with chip on standby or sleep mode depending on idlemode note: initial mode is the chip lowpower mode at sequencer start. 1 fromidle rw 0x00 controls the sequencer transition from the idle state on a t1 interrupt: 0: to transmit state 1: to receive state 0 fromtransmit rw 0x00 controls the sequencer transition from the transmit state: 0: to lowpowerselection on a packetsent interrupt 1: to receive state on a packetsent interrupt name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 103 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regseqconfig2 (0x37) 7-5 fromreceive rw 0x00 controls the sequencer transition from the receive state 000 and 111: unused 001: to packetreceived state on a payloadready interrupt 010: to lowpowerselection on a payloadready interrupt 011: to packetreceived state on a crcok interrupt (1) 100: to sequenceroff state on a rssi interrupt 101: to sequenceroff state on a syncaddress interrupt 110: to sequenceroff state on a preambledetect interrupt irrespective of this setting, transition to lowpowerselection on a t2 interrupt (1) if the crc is wrong (corrupted packet, with crc on but crcautoclearon =0), the payloadready interrupt will drive the sequencer to rxtimeout state. 4-3 fromrxtimeout rw 0x00 controls the state-machine transition from the receive state on a rxtimeout interrupt (and on payloadready if fromreceive = 011): 00: to receive state, via receiverestart 01: to transmit state 10: to lowpowerselection 11: to sequenceroff state note: rxtimeout interrupt is a timeoutrxrssi, timeoutrxpreamble or timeoutsignalsync interrupt 2-0 frompacketreceived rw 0x00 controls the state-machine transition from the packetreceived state: 000: to sequenceroff state 001: to transmit state on a fifoempty interrupt 010: to lowpowerselection 011: to receive via fs mode , if frequency was changed 100: to receive state (no frequency change) regtimerresol (0x38) 7-4 unused r - unused 3-2 timer1resolution rw 0x00 resolution of timer 1 00: timer1 disabled 01: 64 us 10: 4.1 ms 11: 262 ms 1-0 timer2resolution rw 0x00 resolution of timer 2 00: timer2 disabled 01: 64 us 10: 4.1 ms 11: 262 ms regtimer1coef (0x39) 7-0 timer1coefficient rw 0xf5 multiplying coefficient for timer 1 regtimer2coef (0x3a) 7-0 timer2coefficient rw 0x20 multiplying coefficient for timer 2 name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 104 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation service registers regimagecal (0x3b) 7 autoimagecalon rw 0x00 * controls the image calibration mechanism 0 ? calibration of the receiver depending on the temperature is disabled 1 ? calibration of the receiver depending on the temperature enabled. 6 imagecalstart wt - triggers the iq and rssi calibration when set in standby mode. 5 imagecalrunning r 0x00 set to 1 while the image and rssi calibration are running. toggles back to 0 when the process is completed 4 unused r - unused 3 tempchange r 0x00 irq flag witnessing a temperature change exceeding tempthreshold since the last image and rssi calibration: 0 ? temperature change lower than tempthreshold 1 ? temperature change greater than tempthreshold 2-1 tempthreshold rw 0x01 temperature change threshold to trigger a new i/q calibration 00 ? 5 c 01 ? 10 c 10 ? 15 c 11 ? 20 c 0 tempmonitoroff rw 0x00 controls the temperature monitor operation: 0 ? temperature monitoring done in all modes except sleep and standby 1 ? temperature monitoring stopped. regtemp (0x3c) 7-0 te m p va l u e r - measured temperature -1 c per lsb needs calibration for absolute accuracy reglowbat (0x3d) 7-4 unused r - unused 3 lowbaton rw 0x00 low battery detector enable signal 0 ? lowbat detector disabled 1 ? lowbat detector enabled 2-0 lowbattrim rw 0x02 trimming of the lowbat threshold: 000 ? 1.695 v 001 ? 1.764 v 010 ? 1.835 v (d) 011 ? 1.905 v 100 ? 1.976 v 101 ? 2.045 v 110 ? 2.116 v 111 ? 2.185 v status registers name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 105 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regirqflags1 (0x3e) 7 modeready r - set when the operation mode requested in mode , is ready - sleep: entering sleep mode - standby: xo is running - fs: pll is locked - rx: rssi sampling starts - tx: pa ramp-up completed cleared when changing the operating mode. 6 rxready r - set in rx mode, after rssi, agc and afc. cleared when leaving rx. 5 txready r - set in tx mode, after pa ramp-up. cleared when leaving tx. 4 plllock r - set (in fs, rx or tx) when the pll is locked. cleared when it is not. 3 rssi rwc - set in rx when the rssivalue exceeds rssithreshold. cleared when leaving rx or setting this bit to 1. 2 timeout r - set when a timeout occurs cleared when leaving rx or fifo is emptied. 1 preambledetect rwc - set when the preamble detector has found valid preamble. bit clear when set to 1 0 syncaddressmatch rwc - set when sync and address (if enabled) are detected. cleared when leaving rx or fifo is emptied. this bit is read only in packet mode, rwc in continuous mode regirqflags2 (0x3f) 7 fifofull r - set when fifo is full (i.e. contains 66 bytes), else cleared. 6 fifoempty r - set when fifo is empty, and cleared when there is at least 1 byte in the fifo. 5 fifolevel r - set when the number of bytes in the fifo strictly exceeds fifothreshold , else cleared. 4 fifooverrun rwc - set when fifo overrun occurs. (except in sleep mode) flag(s) and fifo are cleared when this bit is set. the fifo then becomes immediately available for the next transmission / reception. 3 packetsent r - set in tx when the complete packet has been sent. cleared when exiting tx 2 payloadready r - set in rx when the payload is ready (i.e. last byte received and crc, if enabled and crcautoclearoff is cleared , is ok). cleared when fifo is empty. 1 crcok r - set in rx when the crc of the payload is ok. cleared when fifo is empty. 0 lowbat rwc - set when the battery voltage drops below the low battery threshold. cleared only when set to 1 by the user. io control registers name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 106 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regdiomapping1 (0x40) 7-6 dio0mapping rw 0x00 mapping of pins dio0 to dio5 see table 17 for mapping in lora mode see table 28 for mapping in continuous mode see table 29 for mapping in packet mode 5-4 dio1mapping rw 0x00 3-2 dio2mapping rw 0x00 1-0 dio3mapping rw 0x00 regdiomapping2 (0x41) 7-6 dio4mapping rw 0x00 5-4 dio5mapping rw 0x00 3-1 reserved rw 0x00 reserved. retain default value 0 mappreambledetect rw 0x00 allows the mapping of either rssi or preambledetect to the dio pins, as summarized on table 28 and table 29 0 ? rssi interrupt 1 ? preambledetect interrupt version register regversion (0x42) 7-0 version r 0x22 version code of the chip. bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. additional registers regagcref (0x43) 7-6 unused r - unused 5-0 agcreferencelevel rw 0x13 sets the floor reference for all agc thresholds: agc reference [dbm] = -174 dbm + 10*log(2* rxbw ) + snr + agcreferencelevel snr = 8 db, fixed value regagcthresh1 (0x44) 7-5 unused r - unused 4-0 agcstep1 rw 0x0e defines the 1st agc threshold regagcthresh2 (0x45) 7-4 agcstep2 rw 0x05 defines the 2nd agc threshold: 3-0 agcstep3 rw 0x0b defines the 3rd agc threshold: regagcthresh3 (0x46) 7-4 agcstep4 rw 0x0d defines the 4th agc threshold: 3-0 agcstep5 rw 0x0b defines the 5th agc threshold: regpllhop (0x4b) 7 fasthopon rw 0x00 bypasses the main state machine for a quick frequency hop. writing regfrflsb will trigger the frequency change. 0 ? frf is validated when fstx or fsrx is requested 1 ? frf is validated triggered when regfrflsb is written 6-0 reserved rw 0x2e reserved regtcxo (0x58) 7-5 reserved rw 0x00 reserved. retain default value 4 tcxoinputon rw 0x00 controls the crystal oscillator 0 ? crystal oscillator with external crystal 1 ? external clipped sine tcxo ac-connected to xta pin 3-0 reserved rw 0x09 reserved. retain default value. regpadac (0x5a) 7-3 reserved rw 0x10 reserved. retain default value 2-0 padac rw 0x04 enables the +20 dbm option on pa_boost pin 0x04 ? default value 0x07 ? +20 dbm on pa_boost when outputpower = 1111 name (address) bits variable name mode default value fsk/ook description
www.semtech.com page 107 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regpll (0x5c) 7-6 pllbandwidth rw 0x03 controls the pll bandwidth: 00 ? 75 khz 10 ? 225 khz 01 ? 150 khz 11 ? 300 khz 5-0 reserved rw 0x10 reserved. retain default value regplllowpn (0x5e) 7-6 pllbandwidth rw 0x03 controls the low phase noise pll bandwidth: 00 ? 75 khz 10 ? 225 khz 01 ? 150 khz 11 ? 300 khz 5-0 reserved rw 0x10 reserved. retain default value regformertemp (0x6c) 7-0 formertemp rw - temperature saved during the latest iq (rssi and image) calibrated. same format as tempvalue in regtemp . regbitratefrac (0x70) 7-4 unused r 0x00 unused 3-0 bitratefrac rw 0x00 fractional part of the bit rate divider (only valid for fsk) if bitratefrac > 0 then: name (address) bits variable name mode default value fsk/ook description bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- =
www.semtech.com page 108 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 6.3. lora tm mode register map this section details the sx1272/73 register mapping and the precise contents of each register in lora tm mode. it is essential to understand that the lora modem is contro lled independently of the fsk modem. therefore, care should be taken when accessing the registers, especially as some register may have the same name in lora or fsk mode. the lora registers are only accessible when the device is set in lora mode (and, in the same way, the fsk register are only accessible in fsk mode). however, in some cases, it may be necessary to access some of the fsk register while in lora mode. to this aim, the accessharedreg bit was created in the regopmode register. this bit, when set to ?1?, will grant access to the fsk register 0x0d up to the register 0x 3f. once the setup has been done, it is strongly recommended to clear this bit so that lora register can be access normally. convention: r: read, w: write, c: set to clear and t: trigger table 41 register map, lora mode name (address) bits variable name mode reset lora tm ? description regfifo (0x00) 7-0 fifo rw 0x00 lora tm base-band fifo data input/output. fifo is cleared an not accessible when device is in sleep mode common register settings regopmode (0x01) 7 longrangemode rw 0x0 0 ? fsk/ook mode 1 ? lora tm mode this bit can be modified only in sleep mode. a write operation on other device modes is ignored. 6 accessharedreg rw 0x0 this bit operates when device is in lora mode; if set it allows access to fsk registers page located in address space (0x0d:0x3f) while in lora mode 0 ? access lora registers page 0x0d: 0x3f 1 ? access fsk registers page (in mode lora) 0x0d: 0x3f 5-3 unused r 0x00 2-0 mode rwt 0x01 device modes 000 ? sleep 001 ? stdby 010 ? frequency synthesis tx (fstx) 011 ? transmit (tx) 100 ? frequency synthesis rx (fsrx) 101 ? receive continuous (rxcontinuous) 110 ? receive single (rxsingle) 111 ? channel activity detection (cad) (0x02) 7-0 reserved r 0x00 - (0x03) 7-0 reserved r 0x00 - (0x04) 7-0 reserved r 0x00 - (0x05) 7-0 reserved r 0x00 - regfrmsb (0x06) 7-0 frf(23:16) rw 0xe4 msb of rf carrier frequency regfrmib (0x07) 7-0 frf(15:8) rw 0xc0 mib of rf carrier frequency
www.semtech.com page 109 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regfrlsb (0x08) 7-0 frf(7:0) rwt 0x00 lsb of rf carrier frequency resolution is 61.035 hz if f(xosc) = 32 mhz. default value is 0xe4c000 = 915 mhz. register values must be modified only when device is in sleep or standby mode. register for rf regpaconfig (0x09) 7 paselect rw 0x00 selects pa output pin 0 ? rfio pin. output power is limited to 13 dbm. 1 ? pa_boost pin. output power is limited to 20 dbm 6-4 unused r - unused 3-0 outputpower rw 0x0f power amplifier max output power: pout = 2 + outputpower(3:0) on pa_boost. pout = -1 + outputpower(3:0) on rfio. regparamp (0x0a) 7-5 unused r - unused 4 lowpntxplloff rw 0x01 1 ? low consumption pll is used in receive and transmit mode 0 ? low consumption pll in receive mode, low phase noise pll in transmit mode. 3-0 paramp(3:0) rw 0x09 rise/fall time of ramp up/down in fsk 0000 ? 3.4 ms 0001 ? 2 ms 0010 ? 1 ms 0011 ? 500 us 0100 ? 250 us 0101 ? 125 us 0110 ? 100 us 0111 ? 62 us 1000 ? 50 us 1001 ? 40 us 1010 ? 31 us 1011 ? 25 us 1100 ? 20 us 1101 ? 15 us 1110 ? 12 us 1111 ? 10 us regocp (0x0b) 7-6 unused r 0x00 unused 5 ocpon rw 0x01 enables overload current protection (ocp) for pa: 0 ? ocp disabled 1 ? ocp enabled 4-0 ocptrim rw 0x0b trimming of ocp current: i max = 45+5*ocptrim [ma] if ocptrim <= 15 (120 ma) / i max = -30+10*ocptrim [ma] if 15 < ocptrim <= 27 (130 to 240 ma) i max = 240ma for higher settings default i max = 100ma name (address) bits variable name mode reset lora tm ? description f rf f(xosc) frf ? 2 19 ----------------- ------------------ - =
www.semtech.com page 110 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation reglna (0x0c) 7-5 lnagain rwx 0x01 lna gain setting: 000 ? not used 001 ? g1 = maximum gain 010 ? g2 011 ? g3 100 ? g4 101 ? g5 110 ? g6 = minimum gain 111 ? not used 4-2 reserved r0x00- 1-0 lnaboost rw 0x00 00 ? default lna current 11 ? boost on, 150% lna current. lora page registers regfifoaddrptr (0x0d) 7-0 fifoaddrptr rw 0x00 spi interface address pointer in fifo data buffer. regfifotxbasead dr (0x0e) 7-0 fifotxbaseaddr rw 0x80 write base address in fifo data buffer for tx modulator regfiforxbasead dr (0x0f) 7-0 fiforxbaseaddr rw 0x00 read base address in fifo data buffer for rx demodulator regfiforxcurrent addr (0x10) 7-0 fiforxcurrentaddr r n/a start address (in data buffer) of last packet received regirqflagsmask (0x11) 7 rxtimeoutmask rw 0x00 timeout interrupt mask: setting this bit ma sks the corresponding irq in regirqflags 6 rxdonemask rw 0x00 packet reception complete interrupt mask: setting this bit masks the corresponding irq in regirqflags 5 payloadcrcerrormask rw 0x00 payload crc error interrupt mask: setting this bit masks the corresponding irq in regirqflags 4 validheadermask rw 0x00 valid header received in rx mask: setting this bit masks the corresponding irq in regirqflags 3 txdonemask rw 0x00 fifo payload transmission complete interrupt mask: setting this bit masks the corresponding irq in regirqflags 2 caddonemask rw 0x00 cad complete interrupt mask: setting this bit masks the corresponding irq in regirqflags 1 fhsschangechannelm ask rw 0x00 fhss change channel interrupt mask: setting this bit masks the corresponding irq in regirqflags 0 caddetectedmask rw 0x00 cad detected interrupt mask: setting this bit masks the corresponding irq in regirqflags name (address) bits variable name mode reset lora tm ? description
www.semtech.com page 111 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regirqflags (0x12) 7 rxtimeout rc 0x00 timeout interrupt: writing a 1 clears the irq 6 rxdone rc 0x00 packet reception complete interrupt: writing a 1 clears the irq 5 payloadcrcerror rc 0x00 payload crc error interrupt: writing a 1 clears the irq 4 validheader rc 0x00 valid header received in rx: writing a 1 clears the irq 3 txdone rc 0x00 fifo payload transmission complete interrupt: writing a 1 clears the irq 2 caddone rc 0x00 cad complete: write to clear: writing a 1 clears the irq 1 fhsschangechannel rc 0x00 fhss change channel interrupt: writing a 1 clears the irq 0 caddetected rc 0x00 valid lora signal detected during cad operation: writing a 1 clears the irq regrxnbbytes (0x13) 7-0 fiforxbytesnb r n/a number of payload bytes of latest packet received regrxheadercnt valuemsb (0x14) 7-0 validheadercntmsb(15: 8) rn/a number of valid headers received since last transition into rx mode, msb(15:8). header and packet counters are reseted in sleep mode. regrxheadercnt valuelsb (0x15) 7-0 validheadercntlsb(7:0) r n/a number of valid headers received since last transition into rx mode, lsb(7:0). header and packet counters are reseted in sleep mode. regrxpacketcntv aluemsb (0x16) 7-0 validpacketcntmsb(15: 8) rc n/a number of valid packets received since last transition into rx mode, msb(15:8). header and packet counters are reseted in sleep mode. regrxpacketcntv aluelsb (0x17) 7-0 validpacketcntlsb(7:0) r n/a number of valid packets received since last transition into rx mode, lsb(7:0). header and packet counters are reseted in sleep mode. regmodemstat (0x18) 7-5 rxcodingrate r n/a coding rate of last header received 4 modemstatus r ?1? modem clear 3 r ?0? header info valid 2 r ?0? rx on-going 1 r ?0? signal synchronized 0 r ?0? signal detected regpktsnrvalue (0x19) 7-0 packetsnr rn/a estimation of snr on last packet received.in two?s compliment format mutiplied by 4. name (address) bits variable name mode reset lora tm ? description snr db >@ packetsnr two s complement >@ 4 ----------------------------------------------------------------------------------- =
www.semtech.com page 112 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regpktrssivalue (0x1a) 7-0 packetrssi r n/a rssi of the latest packet received (dbm) rssi[dbm] = - 139 + packetrssi (when snr >= 0) or rssi[dbm] = - 139 + packetrssi + packetsnr *0.25 (when snr < 0) regrssivalue (0x1b) 7-0 rssi r n/a current rssi value (dbm) rssi[dbm] = - 139 + rssi reghopchannel (0x1c) 7 plltimeout r n/a pll failed to lock while attempting a tx/rx/cad operation 1 ? pll did not lock 0 ? pll did lock 6 crconpayload r n/a crc information extracted from the received packet header (explicit header mode only) 0 ? header indicates crc off 1 ? header indicates crc on 5-0 fhsspresentchannel r n/a current value of frequency hopping channel in use. regmodemconfig 1 (0x1d) 7-6 bw rw 0x0 signal bandwidth: 00 ? 125 khz 01 ? 250 khz 10 ? 500 khz 11 ? reserved 5-3 codingrate rw ?001? error coding rate 001 ? 4/5 010 ? 4/6 011 ? 4/7 100 ? 4/8 all other values ? reserved in implicit header mode should be set on receiver to determine expected coding rate. see section 4.1.1.3. 2 implicitheadermodeon rw 0x0 0 ? explicit header mode 1 ? implicit header mode 1 rxpayloadcrcon rw 0x0 enable crc generation and check on payload: 0 ? crc disable 1 ? crc enable if crc is needed, rxpayloadcrcon should be set: - in implicit header mode: on tx and rx side - in explicit header mode: on the tx side alone (recovered from the header in rx side) 0 lowdatarateoptimize rw 0x0 0 ? disabled 1 ? enabled; mandated for sf11 and sf12 with bw = 125 khz name (address) bits variable name mode reset lora tm ? description
www.semtech.com page 113 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regmodemconfig 2 (0x1e) 7-4 spreadingfactor rw 0x7 sf rate (expre ssed as a base-2 logarithm) 6 ? 64 chips / symbol 7 ? 128 chips / symbol 8 ? 256 chips / symbol 9 ? 512 chips / symbol 10 ? 1024 chips / symbol 11 ? 2048 chips / symbol 12 ? 4096 chips / symbol other values reserved. 3 txcontinuousmode rw 0 0 ? normal mode, a single packet is sent 1 ? continuous mode, send multiple packets across the fifo (used for spectral analysis) 2 agcautoon rw 0x01 0 ? lna gain set by register lnagain 1 ? lna gain set by the internal agc loop 1-0 symbtimeout(9:8) rw 0x00 rx time-out msb regsymbtimeoutl sb (0x1f) 7-0 symbtimeout(7:0) rw 0x64 rx time-out lsb rx operation time-out value expressed as number of symbols: regpreamblemsb (0x20) 7-0 preamblelength(15:8) rw 0x0 preamble length msb, = preamblelength + 4.25 symbols see section 4.1.1.6 for more details. regpreamblelsb (0x21) 7-0 preamblelength(7:0) rw 0x8 preamble length lsb regpayloadlength (0x22) 7-0 payloadlength(7:0) rw 0x1 payload length in bytes. the register needs to be set in implicit header mode for the expected packet length. a 0 value is not permitted regmaxpayloadle ngth (0x23) 7-0 payloadmaxlength(7:0) rw 0xff maximum payload length; if header payload length exceeds value a header crc error is generated. allows filtering of packet with a bad size. reghopperiod (0x24) 7-0 freqhoppingperiod(7:0) rw 0x0 symbol periods between frequency hops. (0 = disabled). 1st hop always happen after the 1st header symbol regfiforxbyteadd r (0x25) 7-0 fiforxbyteaddrptr r n/a current value of rx databuffer pointer (address of last byte written by lora receiver) (0x26) - (0x27) - reserved r n/a reserved regfeimsb (0x28) 7-4 reserved r n/a reserved 3-0 freqerror(19:16) r 0x0 estimated frequency error from modem in 2?s compliment format. msb of rf frequency error (regfeimid (0x29) 7-0 freqerror(15:8) r 0x0 middle byte of rf frequency error name (address) bits variable name mode reset lora tm ? description timeout symbtimeout ts ? = f error freqerror 2 24 u f xtal ----------------------------------------- - =
www.semtech.com page 114 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation regfeilsb (0x2a) 7-0 freqerror(7:0) r 0x0 lsb of rf frequency error (0x2b) - reserved r n/a reserved regrssiwideband (0x2c) 7-0 rssiwideband(7:0) r n/a wideband rssi measurement used to locally generate a random number (0x2d) - (0x30) - reserved r n/a reserved regdetectoptimiz e (0x31) 7-3 reserved r 0xc0 reserved 2-0 detectionoptimize rw 0x03 lora detection optimize 0x03 ? sf7 to sf12 0x05 ? sf6 (0x32) - reserved r n/a reserved reginvertiq (0x33) 7 reserved rw 0x0 reserved 6 invertiq rw 0x0 invert the lora i and q signals 0 ? normal mode 1 ? i and q signals are inverted 5-0 reserved rw 0x27 reserved (0x34) - (0x36) 7-0 reserved r n/a reserved regdetectionthre shold (0x37) 7-0 detectionthreshold rw 0x0a lora detection threshold 0x0a ? sf7 to sf12 0x0c ? sf6 (0x38) - reserved r n/a reserved regsyncword (0x39) 7-0 syncword rw 0x12 lora sync word value 0x34 is reserved for lorawan networks (0x3a) - (0x3f) - reserved r n/a reserved name (address) bits variable name mode reset lora tm ? description
www.semtech.com page 115 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7. application information 7.1. crystal resonator specification ta b l e 42 shows the crystal resonator specific ation for the crys tal reference oscilla tor circuit of the sx1272/73. this specification covers the full range of operation of th e sx1272/73 and is employed in the reference design. table 42 crystal specification symbol description conditions min typ max unit fxosc xtal frequency - 32 - mhz rs xtal serial resistance - 15 40 ohms c0 xtal shunt capacitance - 1.5 3 pf cfoot external foot capacitance on each pin xta and xtb 8 15 22 pf cload crystal load capacitance 6 - 12 pf notes - the initial frequency to lerance, temperature stability and aging performanc e should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected. - the loading capacitance should be applied externally, a nd adapted to the actual cload specification of the xtal. 7.2. reset of the chip a power-on reset of the sx1272/73 is triggered at power up. additio nally, a manual reset can be issued by controlling pin 6. 7.2.1. por if the application requires the disconnection of vdd from the sx1272/73, despite of the extremely low sleep mode current, the user should wait for 10 ms from of the end of the por cycle before commencing communications over the spi bus. pin 6 (reset) should be left floating during the por sequence. wait for 10 ms vdd pin 6 (output) chip is ready from this point on undefined figure 46. por timing diagram please note that any clkout activity can also be used to detect that the chip is ready.
www.semtech.com page 116 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.2.2. manual reset a manual reset of the sx1272/73 is possible even for applicati ons in which vdd cannot be physically disconnected. pin 6 should be pulled high for a hundred microseconds and then rel eased. the user should then wait for 5 ms before using the chip. vdd > 100 us chip is ready from this point on pin 6 ( in p ut ) high-z high-z ??1?? wait for 5 ms figure 47. manual reset timing diagram note whilst pin 6 is driven high an ov er current consumption of up to te n milliampere can be seen on vdd. 7.3. top sequencer: listen mode examples in this scenario the circuit spends most of the time in idle mode during which only the rc oscillator is on. periodically the receiver wakes up and looks for incoming signal. if a wanted signal is detected the receiver is kept on and data are analyzed. otherwise, if there was no wanted signal for a defined period of time, the receiver is switched off until the next receive period. during listen mode the radio stays most of the time in a low power mode resulting in very low average power co nsumption. the general timing diagram of this scenario is given in figure 48 . listen ? mode ? : ? principle receive receive idle ( sleep + rc ) idle figure 48. listen mode: principle an interrupt request is generated on a packet rec eption. the user can then take appropriate action. depending on the application and environment, ther e ar e several ways to implement listen mode: ? wake on a preambledetect interrupt. ? wake on a syncaddress interrupt. ? wake on a payloadready interrupt. 7.3.1. wake on preamble interrupt in one possible scenario, the sequencer polls for a preamble de tection. if a preamble signal is detected, the sequencer is switched off and the circuit stays in receive mode until the user switches modes. otherwise, th e receiver is switched off until the next rx period.
www.semtech.com page 117 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.3.1.1. timing diagram when no signal is received, the circuit wakes every timer1 + t imer2 and switches to receive mode for a time defined by timer2, as shown on the following diagram. if no preamble is detected, it then switches back to idle mode, i.e. sleep mode with rc oscillator on. no ? received ? signal receive receive idle ( sleep + rc ) idle timer2 timer1 timer2 timer1 timer1 figure 49. listen mode with no preamble received if a preamble signal is detected t he sequencer is switched off. the preambledetect signal can be mapped to dio4 in order to request the user's attention. timer2 received ? signal preamble ( as long as t1 + 2 * t2 ) sync word payload crc receive idle ( sleep + rc ) timer1 preamble detect timer2 figure 50. listen mode with preamble received
www.semtech.com page 118 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.3.1.2. sequencer configuration the following graph shows listen mode - wake on preambledetect state machine: state ? machine lowpower selection idle receive lowpowerselection = 1 on t2 on t1 fromidle = 1 on preambledetect fromreceive = 110 sequencer off idlemode = 1 : sleep start sequencer off & initial mode = sleep or standby start bit set fromstart = 00 figure 51. wake on preambledetect state machine this example configuration is achieved as follows: table 43 listen mode with preambledetect condition settings t timer2 defines the maximum duration the chip stays in receive mode as long as no preamble is detected. in order to optimize power consumption timer2 must be set just long enough for preamble detection. t timer1 + t timer2 defines the cycling period, i.e. time between two pr eamble polling starts. in or der to optimize average power consumption, timer1 should be re latively long. however, increasing timer1 also extends packet reception duration. in order to insure packet detection and optimize the receiver's p ower consumption the received packet preamble should be as long as t timer1 + 2 x t timer2 . an example of dio configuration for this mode is described in the following table: table 44 listen mode with preambledetect condition recommended dio mapping variable effect idlemode 1: sleep mode fromstart 00: to lowpowerselection lowpowerselection 1: to idle state fromidle 1: to receive state on t1 interrupt fromreceive 110: to sequencer off on preambledetect interrupt dio value description 001crcok 1 00 fifolevel 300fifoempty 4 11 preambledetect ? note: mappreambledetect bit should be set.
www.semtech.com page 119 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.3.2. wake on syncaddress interrupt in another possible scenario, the sequencer polls for a preamble detection and then for a valid syncaddress interrupt. if events occur, the sequencer is switched off and the circui t stays in receive mode unt il the user switches modes. otherwise, the receiver is switch ed off until the next rx period. 7.3.2.1. timing diagram most of the sequencer running time is spent duty cycling the r eceiver and idle modes with no wanted signal present. as shown by the timing diagram in figure 52 , the circuit wakes periodically for a short tim e, defined by rxtimeout. the circuit is in a low power mode for the rest of timer1 + timer2 (i.e. timer1 + timer2 - trxtimeout) no ? wanted ? signal receive receive idle ( sleep + rc ) idle idle timer2 timer1 timer2 timer1 timer1 rxtimeout rxtimeout figure 52. listen mode with no syncaddress detected if a preamble is detected before rxtimeout timer ends the circuit stays in re ceive mode and wa its for a valid syncaddress detection. if none is detected by the end of timer2, receive mode is deactiva ted and the polling cycl e resumes, without any user intervention. unwanted ? signal preamble ( preamble + sync = t2 ) wrong word payload crc preamble detect receive receive idle idle idle timer2 timer1 timer2 timer1 timer1 rxtimeout rxtimeout figure 53. listen mode with pr eamble received and no syncaddress but if a valid sync word is detected a syncaddress interrupt is fired, the sequencer is switched off and the circuit stays in receive mode as long as the user doesn't switch modes.
wanted ? signal preamble ( preamble + sync = t2 ) sync word payload crc preamble detect receive idle timer2 timer1 sync address fifo level rxtimeout www.semtech.com page 120 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation figure 54. listen mode with preamble received & valid syncaddress 7.3.2.2. sequencer configuration the following graph shows listen mode - wake on syncaddress state machine: state ? machine lowpower selection idle receive rxtimeout lowpowerselection = 1 fromrxtimeout = 10 on rxtimeout on t2 on t1 fromidle = 1 on syncadress fromreceive = 101 sequencer off idlemode = 1 : sleep start fromstart = 00 sequencer off & initial mode = sleep or standby start bit set figure 55. wake on syncaddress state machine this example configuration is achieved as follows: table 45 listen mode with syncaddress condition settings variable effect idlemode 1: sleep mode fromstart 00: to lowpowerselection
www.semtech.com page 121 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation t timeoutrxpreamble should be set to the expected transmit preamble duration (depends on preambledetectsize and bitrate ). t timer1 should be set to 64 s (shortest possible duration). t timer2 is set so that t timer1 + t timer2 defines the time between two start of reception. in order to ensure packet detection and optimize the receiver power consumption th e received packet preamble should be defined so that t preamble = t timer2 - t syncaddress with t syncaddress = ( syncsize + 1 ) *8/ bitrate . an example of dio configuration for this mode is described in the following table: table 46 listen mode with preambledetect condition recommended dio mapping lowpowerselection 1: to idle state fromidle 1: to receive state on t1 interrupt fromreceive 101: to sequencer off on syncaddress interrupt fromrxtimeout 10: to lowpowerselection dio value description 001crcok 1 00 fifolevel 2 11 syncaddress 300fifoempty 4 11 preambledetect ? note: mappreambledetect bit should be set.
www.semtech.com page 122 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.4. top sequencer: beacon mode in this mode, a single message is per iodically re-transmitted. if the paylo ad being sent is always identical and payloadlength is smaller than the fifo size, the use of the beaconon bit in regpacketconfig2 together with the sequencer permit to achieve periodic beacon without any user intervention. 7.4.1. timing diagram in this mode, the radio is switched to transmit mode every t timer1 + t timer2 and back to idle mode after packetsent , as shown in the diagram below. the sequencer insures minimal time is spent in transmit mode and therefore power consumption is optimized. beacon ? mode transmit transmit idle ( sleep + rc ) idle idle timer2 timer1 timer1 timer1 timer2 packet sent packet sent figure 56. beacon mode timing diagram 7.4.2. sequencer configuration the beacon mode state machine is presented in the following graph. it should be noted that the sequencer enters an infinite loop and can only be stopped by setting sequencerstop bit in regseqconfig1 . state ? machine transmit on t1 fromidle = 0 on packetsent fromtransmit = 0 lowpower selection idle lowpowerselection = 1 idlemode = 1 : sleep start fromstart = 00 sequencer off & initial mode = sleep or standby start bit set figure 57. beacon mode state machine
www.semtech.com page 123 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation this example is achieved by programming the sequencer as follows: table 47 beacon mode settings t timer1 + t timer2 define the time between the start of two transmissions. variable effect idlemode 1: sleep mode fromstart 00: to lowpowerselection lowpowerselection 1: to idle state fromidle 0: to transmit state on t1 interrupt fromtransmit 0: to lowpowerselection on packetsent interrupt
www.semtech.com page 124 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.5. example crc calculation the following routine may be implemented to mimic the crc calculation of the sx1272/73: figure 58. example crc code
www.semtech.com page 125 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 7.6. example temperature reading the following routine may be implemented to read the temperature and calibrate the sensor: figure 59. example temperature reading
www.semtech.com page 126 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 8. packaging information 8.1. package outline drawing the sx1272/73 is available in a 28-lead qfn package as shown in figure 60. figure 60. package outline drawing
www.semtech.com page 127 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 8.2. recommended land pattern figure 61. recommended land pattern
www.semtech.com page 128 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 8.3. tape and reel information figure 62. tape and reel information
www.semtech.com page 129 sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation 9. revision history table 48 revision history revision date comment first release. inclusion of fei correction of toa formula improve description in the rssi and iq calibration mechanism correction of default value in fsk added undocumented register corrected rssi formula in lora mode (text +register table clarified operation modes for rx single and rx continuous mode in lora added use cases for rx single and rx continuous mode in lora mode clarified used of lora rxpayloadcrcon in register table added description of register regsyncword in lora register table changed stand-by typo into standby 1 june 2013 2 july 2014 3 october 2014 4 march 2015
www.semtech.com page 130 semtech corporation wireless, sensing & ti ming products division 200 flynn road, ca marillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 e-mail: sales@semtech.com support_rf@semtech.com internet: http://www.semtech.com contact information sx1272/73 wireless, sensing & timing datasheet rev. 3 - march 2015 ?2015 semtech corporation ? semtech 2015 a ll rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed , intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customer?s own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

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